SLRC400 Datasheet, PDF (73/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
9.2 Implementation of the Timer Unit
9.2.1 BLOCK DIAGRAM
The following block diagram shows the timer module.
TStartTxBegin
TxBegin Event
TStartTxEnd
TxEnd Event
TAutoRestart
TRunning
RxEnd Event
TStopRxEnd
RxBegin Event
TStopRxBegin
13.56 MHz
TReloadValue [7:0]
TStartNow
TStopNow
QS
QR
parallel in
start counter /
parallel load
stop counter
Counter Module
(x <= x-1)
TPreScaler [4:0]
Clock
Divider
>clock
parallel out
to Parallel Interface
TimerValue [7:0]
Counter = 0 ?
to Interrupt Logic: TimerIRq
Figure 9-1: Timer Module Block Diagram
The timer unit is designed in a way, that several events in combination with enabling flags start or stop the
counter. For example, setting the bit TstartTxEnd to 1 enables to control the receiving of data using the timer
unit. In addition the first received bit is indicated by TxEndEvent. This combination starts the counter at the
defined TReloadValue.
The timer stops either automatically if the counter value is equal to zero, or if a defined stop event happens
(TautoRestart not enabled).
73
Preliminary