SLRC400 Datasheet, PDF (121/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
19.5.2 AC OPERATING SPECIFICATION
19.5.2.1 Bus Timing for Separated Read/Write Strobe
SYMBOL
tLHLL
tAVLL
tLLAX
tLLWL
tCLWL
tWHCH
tRLDV
tRHDZ
tWLDV
tWHDX
tWLWH
tAVWL
tWHAX
tWHWL
PARAMETER
MIN
ALE pulse width
20
Multiplexed Address Bus valid to ALE low (Address Set Up Time)
15
Multiplexed Address Bus valid after ALE low (Address Hold Time)
8
ALE low to NWR, NRD low
15
NCS low to NRD, NWR low
0
NRD, NWR high to NCS high
0
NRD low to DATA valid
NRD high to DATA high impedance
NWR low to DATA valid
DATA hold after NWR high (Data Hold Time)
8
NRD, NWR pulse width
65
Separated Address Bus valid to NRD, NWR low (Set Up Time)
30
Separated Address Bus valid after NWR high (Hold Time)
8
period between sequenced read / write accesses
150
MAX
65
20
35
Table 19-10: Timing Specification for Separated Read/Write Strobe
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE
t_LHLL
NCS
t
CLWL
t_WHCH
NWR
NRD
t_WHWL
t_LLWL
t_WLWH
t_WHWL
D0 ... D7
t_AVLL
t_LLAX
Multiplexed Addressbus
A0 ... A2
t_WLDV
t_RLDV
D0 ... D7
t_WHDX
t_RHDZ
t_AVWL
t _WHAX
A0 ... A2
Separated Addressbus
A0 ... A2
Figure 19-1: Timing Diagram for Separated Read/Write Strobe
Note: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus
don’t care.
For the multiplexed address and data bus the address lines A0 to A2 have to be connected as described in 4.3.
121
Preliminary