SLRC400 Datasheet, PDF (42/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
5.2.4.8 ClockQControl Register
controls clock generation for the 90° phase shifted Q-channel clock.
Name: ClockQControl
Address: 0x1F
Reset value: 000XXXXX, 0xXX
7
6
5
4
3
2
1
0
ClkQ180Deg ClkQCalib
0
ClkQDelay
Access
r
Rights
r/w
r/w
dy
dy
dy
dy
dy
Description of the bits
Bit
Symbol
7
ClkQ180Deg
6
ClkQCalib
5
0
4-0
ClkQDelay
Function
If the Q-clock is phase shifted more than 180° compared to the I-clock, this bit is
set to 1, otherwise it is 0.
If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and
after data reception from the label.
If this bit is set to 1, no calibration is performed automatically.
This value shall not be changed
This register shows the number of delay elements actually used to generate a 90°
phase shift of the I-clock to obtain the Q-clock.
It can be written directly by the µ-Processor or by the automatic calibration cycle.
42
Preliminary