SLRC400 Datasheet, PDF (79/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
10 POWER REDUCTION MODES
10.1 Hard Power Down
A Hard Power Down is enabled with HIGH on pin RSTPD. This turns off all internal current sinks including
the oscillator. All digital input buffers are separated from the input pads and defined internally (except pin
RSTPD itself). The output pins are frozen at a certain value.
This is shown in the following table:
SYMBOL PIN
OSCIN
1
IRQ
2
RFU
3
SIGOUT
4
TX1
5
TX2
7
NWR
9
NRD
10
NCS
11
D0 to D7 13 to 20
ALE
21
A0
22
A1
23
A2
24
AUX
27
RX
29
VMID
30
RSTPD
31
OSCOUT 32
TYPE
I
O
I
O
O
O
I
I
I
I/O
I
I/O
I
I
O
I
A
I
O
DESCRIPTION
Not separated from input, pulled to AVSS
High impedance
Separated from Input
LOW
HIGH
LOW
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
Separated from Input
High impedance
Not changed
Pulled to AVDD
Not changed
HIGH
Table 10-1: Signal on Pins during Hard Power Down
10.2 Soft Power Down
This mode is immediately entered by setting bit PowerDown in the Control-Register. All internal current sinks
are switched off (including the oscillator buffer).
Different from the Hard Power Down Mode, the digital input buffers are not separated from the input pads but
keep their functionality. The digital output pins do not change their state.
After resetting bit PowerDown in the Control-Register it needs 512 clocks until the Soft Power Down mode is
left. This is indicated by the PowerDown bit itself. Resetting it does not immediately clear it, but it is cleared
automatically by the SL RC400 when the Soft Power Down Mode is left.
Note: If the internal oscillator is used, you have to take into account that it is supplied by AVDD and it will
take a certain time t_osc until the oscillator is stable.
79
Preliminary