SLRC400 Datasheet, PDF (12/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
4 PARALLEL INTERFACE
4.1 Overview of Supported µ-Processor Interfaces
The SL RC400 supports direct interfacing of various µ-Processor. Alternatively the Enhanced Parallel Port
(EPP) of personal computers can be connected directly.
The following table shows the parallel interface signals supported by the SL RC400:
Bus Control Signals
Bus Separated Address and Data Bus Multiplexed Address and Data Bus
Separated Read and Write
Strobes
control
address
NRD, NWR, NCS
A0, A1, A2
NRD, NWR, NCS, ALE
AD0, AD1, AD2, (AD3, AD4, AD5)
data
D0 … D7
AD0 … AD7
Common Read and Write
Strobe
control
address
data
R/NW, NDS, NCS
A0, A1, A2
D0 … D7
R/NW, NDS, NCS, AS
AD0, AD1, AD2, (AD3, AD4, AD5)
AD0 … AD7
control
Common Read and Write
Strobe with Handshake _address
-
(EPP)
data
nWrite, nDStrb, NCS, nAStrb, nWait
AD0, AD1, AD2, (AD3, AD4, AD5)
AD0 … AD7
Table 4-1: Supported µ-Processor Interface Signals
4.2 Automatic µ-Processor Interface Type Detection
After each Power-On or Hard Reset, the SL RC400 also resets its parallel µ-Processor interface mode and
checks the current µ-Processor interface type.
The SL RC400 identifies the µ-Processor interface by means of the logic levels on the control pins after the
Reset Phase. This is done by a combination of fixed pin connections (see below) and a dedicated
initialisation routine (see 11.4).
12
Preliminary