SLRC400 Datasheet, PDF (15/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
4.3.3 COMMON READ/WRITE STROBE AND HAND-SHAKE MECHANISM: EPP
LOW
HIGH
HIGH
nWait
Multiplexed Address/Data (AD1...AD8)
Address Strobe (nAStrb)
Data Strobe (nDStrb)
Read/Write (nWrite)
SL RC400
NCS
A2
A1
A0
D0...D7
ALE
NRD
NWR
Figure 4-3: Connection to µ-Processors with Common Read/Write Strobes and Hand-Shake
For timing specification refer to chapter 19.5.2.3.
Remarks for EPP:
Although in the standard for the EPP no chip select signal is defined, the N_CS of the SL RC400 allows
inhibiting the nDStrb signal. If not used, it shall be connected to DVSS.
After each Power-On or Hard Reset the nWait signal (delivered at pin A0) is high impedance. nWait will be
defined at the first negative edge applied to nAStrb after the Reset Phase.
The SL RC400 does not support Read Address Cycle.
15
Preliminary