SLRC400 Datasheet, PDF (16/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
5 SL RC400 REGISTER SET
5.1 SL RC400 Registers Overview
Page
Addresshex
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Register Name
Page
Command
FIFOData
PrimaryStatus
FIFOLength
SecondaryStatus
InterruptEn
InterruptRq
Page
Control
ErrorFlag
Collpos
TimerValue
CRCResultLSB
CRCResultMSB
PreSet0F
Page
TxControl
CwConductance
ModConductance
CoderControl
ModWidth
ModWidthSOF
PreSet17
Page
RxControl1
DecoderControl
BitPhase
RxThreshold
PreSet1D
RxControl2
ClockQControl
Function
selects the register page
starts (and stops) the command execution
in- and output of 64 byte FIFO buffer
status flags of the receiver and transmitter and of the FIFO buffer
number of bytes buffered in the FIFO
diverse status flags
control bits to enable and disable passing of interrupt requests
interrupt request flags
selects the register page
diverse control flags e.g.: timer, power saving
error flags showing the error status of the last command executed
bit position of the first bit collision detected on the RF-interface
actual value of the timer
LSB of the CRC-Coprocessor register
MSB of the CRC-Coprocessor register
these values shall not be changed
selects the register page
controls the logical behaviour of the antenna driver pins TX1 and TX2
selects the conductance of the antenna driver pins TX1 and TX2
selects the conductance of the antenna driver pins TX1 and TX2 during
modulation
Selects the bit coding mode and the framing during transmission
selects the width of the modulation pulse
selects the width of the modulation pulse for SOF (I•CODE Fast-Mode)
these values shall not be changed
selects the register page
controls receiver behaviour
controls decoder behaviour
selects the bit-phase between transmitter and receiver clock
selects thresholds for the bit decoder
these values shall not be changed
controls decoder behaviour and defines the input source for the receiver
controls clock generation for the 90° phase shifted Q-channel clock
16
Preliminary