SLRC400 Datasheet, PDF (123/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
19.5.2.3 Bus Timing for EPP
SYMBOL
tLLLH
tAVLH
tLHAX
tCLSL
tSHCH
tSLDV,R
tSHDZ
tSLDV,W
tSHDX
tSHRX
tSLSH
tRVSL
tSLWH
tSHWL
PARAMETER
MIN
nAStrb pulse width
20
Multiplexed Address Bus valid to nAStrb high (Set Up Time)
15
Multiplexed Address Bus valid after nAStrb high (Hold Time)
8
NCS low to nDStrb low
0
nDStrb high to NCS high
0
nDStrb low to DATA valid (read cycle)
nDStrb low to DATA high impedance (read cycle)
nDStrb low to DATA valid (write cycle, Set up Time)
DATA hold after nDStrb high (write cycle, Hold Time)
8
nWrite hold after nDStrb high
8
nDStrb pulse width
65
nWrite valid to nDStrb low
8
nDStrb low to nWait high
nDStrb high to nWait low
MAX
65
20
35
75
75
Table 19-12: Timing Specification for Common Read/Write Strobe
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NCS
nWrite
t _CLSL
t_RVSL
t_SHCH
t_SHRX
nDStrb
nAStrb
D0 ... D7
t _SLSH
t _SLDV,R
t _SLDV,W
D0 ... D7
A0 ... A7
t_SHDX
t_SHDZ
nWait
t_SLWH
t_SHWL
Figure 19-3: Timing Diagram for Common Read/Write Strobe
Remark: The figure does not distinguish between the Address Write Cycle and a Data Write Cycle. Take in
account, that timings for the Address Write and Data Write Cycle different. For the EPP-Mode the address
lines A0 to A2 have to be connected as described in 4.3.
123
Preliminary