SLRC400 Datasheet, PDF (108/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
16.6.2.2 CRC-Coprocessor Settings
For the CRC-Coprocessor the following parameters may be configured:
Parameter
CRC Register Length
CRC Algorithm
Bit-Processing Direction
CRC Preset Value
Value
8 Bit or 16 Bit CRC
1 = Algorithm according ISO 15693 or according
ISO/IEC3309
0 = algorithm according to I•CODE1
Shift the MSBit or LSBit first into the CRC-
register
Any
Bit
CRC8
CRC3309
CRCMSBFirst
CRCPresetLSB,
CRCPresetMSB
Table 16-5: CRC-Coprocessor Parameters
Register
ChannelRedundancy
ChannelRedundancy
ChannelRedundancy
CRCPresetLSB,
CRCPresetMSB
The CRC polynomial for the 8-bit CRC is fixed to x⁸ + x⁴ + x³ + x² +1.
The CRC polynomial for the 16-bit CRC is fixed to x¹⁶ + x¹² + x⁵ + 1.
16.6.2.3 Status Flags of the CRC-Coprocessor
The status flag CRCReady indicates, that the CRC-Coprocessor has finished processing of all data bytes
found in the FIFO buffer. With the CRCReady flag setting to 1, an interrupt is requested with TxIRq being set.
This supports interrupt driven usage of the CRC-Coprocessor.
When CRCReady and TxIRq are set to 1, respectively, the content of the CRCResultLSB- and
CRCResultMSB-register and the flag CRCErr is valid.
The CRCResultLSB- and CRCResultMSB-register hold the content of the CRC register, the CRCErr flag
indicates CRC validity for the processed data.
16.7 Error Handling during Command Execution
If any error is detected during command execution, this is shown by setting the status flag Err in the
PrimaryStatus Register. For information about the cause of the error, the µ-Processor may evaluate the
status flags in the ErrorFlag Register.
Error Flag of the ErrorFlag Register
AccessError
FIFOOvl
CRCErr
FramingErr
CollErr
Related to Command
WriteE2, ReadE2, LoadConfig
Not related to a command
Receive, Transceive, CalcCRC
Receive, Transceive
Receive, Transceive
Table 16-6: Error Flags Overview
108
Preliminary