SLRC400 Datasheet, PDF (44/130 Pages) NXP Semiconductors – I·CODE Reader IC

Philips Semiconductors
I•CODE Reader IC
Product Specification Rev. 2.0 November 2001
SL RC400
5.2.5.3 ChannelRedundancy Register
Selects kind and mode of checking the data integrity on the RF-channel.
Name: ChannelRedundancy
Address: 0x22
Reset value: 00001100, 0x0C
7
6
5
4
3
2
1
0
0
CRCMSB CRC CRC8 RxCRCEn TxCRCEn
0
0
First
3309
Access
r/w
r/w
r/w
r/w
r/w
Rights
r/w
r/w
r/w
Description of the bits
Bit
Symbol
Function
7
0
This value shall not be changed
6
CRCMSBFirst If set to 1, CRC-calculation shifts the MSBit into the CRC-Coprocessor first.
If set to 0, CRC-calculation starts with the LSBit.
Note: For usage according ISO 15693 and I?CODE1 this bit has to be 0.
5
CRC 3309 If set to 1, CRC-calculation is done according ISO/IEC3309 as it is defined in
ISO 15693.
Note: For usage according to I•CODE1 this bit has to be 0.
4
CRC8
If set to 1, an 8-bit CRC is calculated.
If set to 0, a 16-bit CRC is calculated.
3
RxCRCEn If set to 1, the last byte(s) of a received frame is/are interpreted as CRC byte/s.
If the CRC itself is correct the CRC byte(s) is/are not passed to the FIFO.
In case of an error, the CRCErr flag is set.
If set to 0, no CRC is expected.
2
TxCRCEn If set to 1, a CRC is calculated over the transmitted data and the CRC byte(s) are
appended to the data stream.
If set to 0, no CRC is transmitted.
1-0
00
RFU
44
Preliminary