PDI1394P21 Datasheet, PDF (8/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
8.0 ABSOLUTE MAXIMUM RATINGS ¹
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
CONDITION
LIMITS
MIN
MAX
UNIT
V_DD
V_I
V_I–5V
V_O
DC supply voltage
DC input voltage
5 volt tolerant input voltage range
DC output voltage range at any output
Electrostatic discharge
Human Body Model
Machine Model
–0.5
4.0
V
–0.5
V_DD+0.5
V
–0.5
5.5
V
–0.5
V_DD+0.5
V
2
kV
200
V
T_amb Operating free-air temperature range
0
+70
°C
T_stg
Storage temperature range
–65
+150
°C
NOTE:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “Recommended Operating
Conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
9.0 RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
V_DD Supply voltage
Source power node
Non-source power node
3.0
2.7 ¹
V_IH
High-level input voltage, pins
CTLn, Dn, C/LKON ²
/ISO = V_DD, V_DD = 2.7 V
/ISO = V_DD, V_DD >= 3.0 V
2.3
2.6
V_IL
Low-level input voltage, pins
CTLn, Dn, C/LKON ²
/ISO = V_DD
I_OH/I_OL
Output current, pins CTLn, Dn,
C/LKON and SYSCLK
V_OH = V_DD –0.5 V, V_OL = 0.5 V
–12
I_O
Output current
TPBIAS outputs
–6
TPA, TPB cable inputs, during data reception
118
V_ID
Differential input voltage amplitude
TPA, TPB cable inputs, during data arbitration
168
V_IC-100
TPB common-mode input voltage
Speed signalling off ^{Source power node}
or S100 speed signal _{Non-source power node}
1.165
1.165
V_IC-200 TPB common-mode input voltage S200 speed signal
Source power node
Non-source power node
0.935
0.935
V_IC-100 TPB common-mode input voltage S400 speed signal
Source power node
Non-source power node
0.523
0.523
t_PU
Power–up reset time
Set by capacitor between /RESET pin and GND
2
TPA, TPB cable inputs, S100 operation
Receive input jitter
TPA, TPB cable inputs, S200 operation
TPA, TPB cable inputs, S400 operation
Between TPA and TPB cable inputs, S00 operation
Receive input skew
Between TPA and TPB cable inputs, S200 operation
Between TPA and TPB cable inputs, S400 operation
f_XTAL
Crystal or external clock frequency
Crystal connected according to Figure 8 or external
clock input at pin XI
24.5735
NOTES:
1. For a node that does not source power to the bus (see Section 4.2.2.2 in the IEEE 1394-1995 standard).
2. C/LKON is only an input when /RESET = 0.
TYP
3.3
3.0
24.576
MAX
3.6
3.6
5.5
5.5
0.7
12
2.5
260
265
2.515
2.015 ¹
2.515
2.015 ¹
2.515
2.015 ¹
1.08
0.5
0.315
0.8
0.55
0.5
24.5785
UNIT
V
V
V
V
V
mA
mA
mV
mV
V
V
V
V
V
V
ms
ns
ns
ns
ns
ns
ns
MHz
1999 Jul 09
8