PDI1394P21 Datasheet, PDF(23/28 Page) NXP Semiconductors

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PDI1394P21 Datasheet, PDF (23/28 Pages) NXP Semiconductors – 3-port physical layer interface

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Philips Semiconductors

3-port physical layer interface

Objective specification

PDI1394P21

18.3 Receive

Whenever the PHY detects the data-prefix state on the serial bus, it

initiates a receive operation by asserting Receive on the CTL terminals

and a logic 1 on each of the D terminals (âdata-onâ indication). The

PHY indicates the start of a packet by placing the speed code

(encoded as shown in Table 17) on the D terminals, followed by

packet data. The PHY holds the CTL terminals in the Receive state

until the last symbol of the packet has been transferred. The PHY

indicates the end of packet data by asserting Idle on the CTL

terminals. All received packets are transferred to the LLC. Note that

the speed code is part of the PHY-LLC protocol and is not included in

the calculation of CRC or any other data protection mechanisms.

Table 17. Speed Code for the Receiver

D0âD7

DATA RATE

0000 0000

S100

0100 0000

S200

0101 0000

S400

1111 1111

âdata-onâ indication

It is possible for the PHY to receive a null packet, which consists of

the data-prefix state on the serial bus followed by the data-end state,

without any packet data. A null packet is transmitted whenever the

packet speed exceeds the capability of the receiving PHY, or

whenever the LLC immediately releases the bus without transmitting

any data. In this case, the PHY will assert Receive on the CTL

terminals with the âdata-onâ indication (all 1âs) on the D terminals,

followed by Idle on the CTL terminals, without any speed code or

data being transferred. In all cases, in normal operation, the

PDI1394P21 sends at least one âdata-onâ indication before sending

the speed code or terminating the receive operation.

The PDI1394P21 also transfers its own self-ID packet, transmitted

during the self-ID phase of bus initialization to the LLC. This packet

is transferred to the LLC just as any other received self-ID packet.

The sequence of events for a normal packet reception is as follows:

â¢ Receive operation initiated. The PHY indicates a receive

operation by asserting Receive on the CTL lines. Normally, the

interface is idle when receive is asserted. However, the receive

operation may interrupt a status transfer operation that is in

progress so that the CTL lines may change from status to receive

without an intervening idle.

â¢ Data-on indication. The PHY may assert the data-on indication code

on the D lines for one or more cycles preceding the speed code.

â¢ Speed code. the PHY indicates the speed of the received packet

by asserting a speed code on the D lines for one cycle

immediately preceding packet data. The link decodes the speed

code on the first Receive cycle for which the D lines are not the

data-on code. If the speed code is invalid, or indicates a speed

higher than that which the link is capable of handling, the link

should ignore the subsequent data.

â¢ Receive data. Following the data-on indication (if any) and the

speed code, the PHY asserts packet data on the D lines with

receive on the CTL lines for the remainder of the receive operation.

â¢ Receive operation terminated. The PHY terminates the receive

operation by asserting the idle on the CTL lines. The PHY asserts

at least one cycle of idle following a receive operation.

SYSCLK

CTL0, CTL1

D0âD7

(a)

(b)

FF (âdata-onâ)

(c)

(d)

SPD

NOTE: SPD = Speed code; see Table 17; d0âdn = Packet data.

Figure 12. Normal Packet Reception Timing

(e)

SV01760

1999 Jul 09

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