PDI1394P21 Datasheet, PDF (14/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
The Port Status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the
Page_Select field and the desired port number to the Port_Select field in base register 7. The configuration of the port status page registers is
shown in Table 3 and corresponding field descriptions given in Table 4. If the selected port is unimplemented, all registers in the port status page
are read as 0.
Table 3. Page 0 (Port Status) Register Configuration
BIT POSITION
ADDRESS
0
1
2
3
4
1000
AStat
BStat
Ch
1001
Peer_Speed
PIE
Fault
1010
Reserved
1011
Reserved
1100
Reserved
1101
Reserved
1110
Reserved
1111
Reserved
5
6
7
Con
Bias
Dis
Reserved
Table 4. Page 0 (Port Status) Register Field Descriptions
FIELD
SIZE TYPE
DESCRIPTION
AStat
2
Rd TPA line state. This field indicates the TPA line state of the selected port, encoded as follows:
Code
11
01
10
00
Arb Value
Z
1
0
invalid
BStat
2
Rd TPB line state. This field indicates the TPB line state of the selected port. This field has the same
encoding as the ASTAT field.
Ch
1
Rd Child/parent status. A 1 indicates that the selected port is a child port. A 0 indicates that the selected
port is the parent port. A disconnected, disabled, or suspended port is reported as a child port. The Ch
bit is invalid after a bus-reset until tree-ID has completed.
Con
1
Rd Debounced port connection status. This bit indicates that the selected port is connected. The
connection must be stable for the debounce time of 330ms–350ms for the Con bit to be set to 1. The
Con bit is reset to 0 by hardware reset and is unaffected by bus reset.
NOTE: The Con bit indicates that the port is physically connected to a peer PHY, but the port is not
necessarily active.
Bias
1
Rd Debounced incoming cable bias status. A 1 indicates that the selected port is detecting incoming cable
bias. The incoming cable bias must be stable for the debounce time of 41.6µs–52µs for the Bias bit to
be set to 1.
Dis
1
Rd/Wr Port disabled control. If 1, the selected port is disabled. The Dis bit is reset to 0 by hardware reset (all
ports are enabled for normal operation following hardware reset). The Dis bit is not affected by bus
reset.
Peer_Speed
3
Rd Port peer speed. This field indicates the highest speed capability of the peer PHY connected to the
selected port, encoded as follows:
Code
000
001
010
011–111
Peer Speed
S100
S200
S400
invalid
The Peer_Speed field is invalid after a bus reset until self-ID has completed.
NOTE: Peer speed codes higher than 010b (S400) are defined in P1394a. However, the PDI1394P21
is only capable of detecting peer speeds up to S400.
PIE
1
Rd/Wr Port event interrupt enable. When set to 1, a port event on the selected port will set the port event
interrupt (PEI) bit and notify the link. this bit is reset to 0 by a hardware reset, and is unaffected by
bus-reset.
Fault
1
Rd/Wr Fault. This bit indicates that a resume-fault or suspend-fault has occurred on the selected port, and that
the port is in the suspended state. A resume-fault occurs when a resuming port fails to detect incoming
cable bias from its attached peer. A suspend-fault occurs when a suspending port continues to detect
incoming cable bias from its attached peer. Writing 1 to this bit clears the fault bit to 0. This bit is reset to
0 by hardware reset and is unaffected by bus reset.
1999 Jul 09
14