PDI1394P21 Datasheet, PDF (3/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
4.0 PIN CONFIGURATION
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LREQ 1
60 AGND
SYSCLK 2
59 TPBIAS2
DGND 3
58 TPA2+
CTL0 4
57 TPA2–
CTL1 5
56 TPB2+
DVDD 6
55 TPB2–
D0 7
54 AVDD
D1 8
53 TPBIAS1
NC 9
52 TPA1+
D2 10
D3 11
PDI1394P21
51 TPA1–
50 TPB1+
D4 12
49 TPB1–
D5 13
48 AVDD
D6 14
47 AVDD
D7 15
46 TPBIAS0
DGND 16
45 TPA0+
CNA 17
44 TPA0–
PD 18
43 TPB0+
LPS 19
42 TPB0–
DGND 20
41 AGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
5.0 PIN DESCRIPTION
Name
Pin Type
Pin Numbers
AGND
Supply
36, 37, 38, 39, 40,
41, 60, 61, 64, 65
AVDD
Supply
34, 35, 47, 48, 54,
62, 63
CNA
CPS
CTL0,
CTL1
CMOS
17
CMOS
27
CMOS 5V tol 4, 5
SV001742
I/O
Description
—
Analog circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
—
Analog circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and DVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
O
Cable Not Active output. This terminal is asserted high when there are
no ports receiving incoming bias voltage.
I
Cable Power Status input. This terminal is normally connected to cable
power through a 370–410 kΩ resistor. This circuit drives an internal
comparator that is used to detect the presence of cable power.
I/O
Control I/Os. These bi-directional signals control communication
between the PDI1394P21 and the LLC. Bus holders are built into
these terminals.
1999 Jul 09
3