PDI1394P21 Datasheet, PDF (22/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
18.2 Status transfer
A status transfer is initiated by the PHY when there is status
information to be transferred to the LLC. The PHY waits until the
interface is idle before starting the transfer. The transfer is initiated
by the PHY asserting Status (01b) on the CTL terminals, along with
the first two bits of status information on the D[0:1] terminals. The
PHY maintains CTL = Status for the duration of the status transfer.
The PHY may prematurely end a status transfer by asserting
something other than Status on the CTL terminals. This occurs if a
packet is received before the status transfer completes. The PHY
continues to attempt to complete the transfer until all status
information has been successfully transmitted. There is at least one
idle cycle between consecutive status transfers.
The PHY normally sends just the first four bits of status to the LLC.
These bits are status flags that are needed by the LLC state
machines. The PHY sends an entire 16-bit status packet to the LLC
after a read register request, or when the PHY has pertinent
information to send to the LLC or transaction layers. The only
defined condition where the PHY automatically sends a register to
the LLC is after self-ID, where the PHY sends the physical-ID
register that contains the new node address. All status transfers are
either 4 or 16 bits unless interrupted by a received packet. The
status flags are considered to have been successfully transmitted to
the LLC immediately upon being sent, even if a received packet
subsequently interrupts the status transfer. Register contents are
considered to have been successfully transmitted only when all
8 bits of the register have been sent. A status transfer is retried after
being interrupted only if any status flags remain to be sent, or if a
register transfer has not yet completed.
The definition of the bits in the status transfer is shown in Table 16,
and the timing is shown in Figure 11.
The sequence of events for a status transfer is as follows:
• Status transfer initiated. the PHY indicates a status transfer by
asserting status on the CTL lines along with the status data on the
D0 and D1 lines (only 2 bits of status are transferred per cycle).
Normally (unless interrupted by a receive operation), a status
transfer will be either 2 or 8 cycles long. A 2-cycle (4 bit) transfer
occurs when only status information is to be sent. An 8-cycle
(16 bit) transfer occurs when register data is to be sent in addition
to any status information.
• Status transfer terminated. The PHY normally terminates a status
transfer by asserting idle on the CTL lines. If a bus reset is
pending, the PHY may also assert Grant on the CTL line
immediately following a complete status transfer.
Table 16. Status Bits
BIT(S)
NAME
0 Arbitration Reset Gap
1 Subaction gap
2 Bus reset
3 Interrupt
4–7 Address
8–15 Data
DESCRIPTION
Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
defined in the IEEE 1394–1995 standard). This bit is used by the LLC in the busy/retry state machine.
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in the
IEEE 1394–1995 standard). This bit is used by the LLC to detect the completion of an isochronous cycle.
Indicates that the PHY has entered the bus reset state.
Indicates that a PHY interrupt event has occurred. An interrupt event may be a configuration time-out, a
cable-power voltage falling too low, a state time-out, or a port status change.
This field holds the address of the PHY register whose contents are being transferred to the LLC.
This field holds the register contents.
SYSCLK
CTL0, CTL1
D0, D1
(a)
00
01
(b)
00
01
00
S[0:1]
S[14:15]
Figure 11. Status Transfer Timing
00
SV01759
1999 Jul 09
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