PDI1394P21 Datasheet, PDF (12/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
16.0 INTERNAL REGISTER CONFIGURATION
There are 16 accessible internal registers in the PDI1394P21. The
configuration of the registers at addresses 0 through 7 (the base
registers) is fixed, while the configuration of the registers at
addresses 8h through Fh (the paged registers) is dependent upon
which one of eight pages, numbered 0h through 7h, is currently
selected. The selected page is set in base register 7h.
The configuration of the base registers is shown in Table 1, and
corresponding field descriptions are given in Table 2. The base
register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in
the following register configuration tables) is read as 0, but is subject
to future usage. All registers in address pages 2 through 6 are
reserved.
Table 1. Base Register Configuration
ADDRESS
0000
0001
0010
0011
0100
0101
0110
0111
0
1
RHB
L
RPIE
IBR
Extended (111b)
PHY_Speed (010b)
C
ISBR
Page_Select
BIT POSITION
2
3
4
5
6
Physical ID
R
Gap_Count
Rsvd
Num_Ports (0011b)
Rsvd
Delay (0000b)
Jitter (000)
Pwr_Class
CTOI
CPSI
STOI
PEI
EAA
Reserved
Rsvd
Port Select
7
CPS
EMC
Table 2. Base Register Field Descriptions
FIELD
SIZE TYPE
DESCRIPTION
Physical ID
6
Rd This field contains the physical address ID of this node determined during self–ID. The physical-ID is
invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status
transfer.
R
1
Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to
1 during tree-ID if this node becomes root.
CPS
1
Rd Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally
tied to serial bus cable power through a 370 kΩ–410 kΩ resistor. A 0 in this bit indicates that the cable
power voltage has dropped below its threshold for ensured reliable operation.
RHB
1
Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB
bit is reset to 0 by a hardware reset, and is unaffected by a bus reset.
IBR
1 Rd/Wr Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set will complete before the bus reset is
initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset.
Gap_Count
6
Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay
times. The gap count can be set either by a write to the register, or by reception or transmission of a
PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus
resets without an intervening write to the gap count register (either by a write to the PHY register or by
a PHY_CONFIG packet).
Extended
3
Rd Extended register definition. For the PDI1394P21, this field is 111b, indicating that the extended register
set is implemented.
Num_Ports
4
Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P21
this field is 3.
PHY_Speed
3
Rd PHY speed capability. For the PDI1394P21, this field is 010b, indicating S400 speed capability.
Delay
4
Rd PHY repeater data delay. This field indicates the worst case repeater data delay for this PHY,
expressed as 144+(delay × 20) ns. For the PDI1393P21, this field is 0.
L
1
Rd/Wr Link active status. This bit indicates that this node’s link is active. The logical AND of this bit and the
LPS active status is replicated in the L field (bit 9) of the self-ID packet. This bit is set to 1 by a
hardware reset and is unaffected by a bus reset.
C
1
Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the “c” field (bit 20) of the self-ID packet. This bit is set to the state
specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset.
Jitter
3 Rd
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest
repeater data delay, expressed as (Jitter + 1) × 20 ns. For the PDI1394P21, this field is 0.
1999 Jul 09
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