PDI1394P21 Datasheet, PDF (16/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
17.0 APPLICATION INFORMATION
PDI1394P21
CABLE PORT
CPS
TPBIAS
400K
0.3–1.0 µF
TPAn+
TPAn–
56Ω 56Ω
TPBn+
TPBn–
56Ω 56Ω
220pF
5 kΩ
CABLE
POWER
PAIR
CABLE
PAIR A
CABLE
PAIR B
OUTER SHIELD
TERMINATION
SV01744
The IEEE Std 1394–1995 calls for a 250 pF capacitor, which is a non-standard component value. A 220 pF capacitor is recommended.
Figure 4. Twisted pair cable interface connections
1 MΩ
0.01 µF
OUTER CABLE SHIELD
0.001 µF
CHASSIS GROUND
SV01748
Figure 5. Typical outer shield termination
0.001 µF
3 _DGND
0.1 µF
V_DD
6 _DVDD
SV01781
Use one of these networks per side for all digital power and ground
pins and one per side for all analog power and ground pins. Place
the network as close to the PHY as possible.
Figure 6. Power supply decoupling network
1 kΩ
LINK POWER
LPS
SQUARE WAVE INPUT
LPS
1 kΩ
SV01750
Figure 7. Non-isolated connection variations for LPS
1999 Jul 09
16