PDI1394P21 Datasheet, PDF (4/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
Name
Pin Type
Pin Numbers
I/O
C/LKON CMOS 5V tol 22
I/O
DGND
D0–D7
DVDD
Supply
3, 16, 20, 21, 28,
—
70, 80
CMOS 5V tol 7, 8, 10, 11, 12, 13,
I/O
14, 15
Supply
6, 29, 30, 68, 69, 79
—
/ISO
CMOS
26
I
LPS
CMOS 5V tol 19
I
LREQ
CMOS 5V tol 1
I
NC
No Connect 9, 31, 71, 72
—
PC0, PC1, CMOS 5V tol 23, 24, 25
I
PC2
PD
CMOS 5V tol 18
I
PLLGND
Supply
74, 75
—
PLLVDD
Supply
73
—
Description
Bus Manager Contender programming input and link-on output. On
hardware reset, this terminal is used to set the default value of the
contender status indicated during self-ID. Programming is done by tying
the terminal through a 10kΩ resistor to a high (contender) or low (not
contender). The resistor allows the link-on output to override the input.
Following hardware reset, this terminal is the link-on output, which is
used to notify the LLC to power-up and become active. The link-on
output is a square-wave signal with a period of approximately 163 ns (8
SYSCLK cycles) when active. The link-on output is deasserted low when
the LPS input terminal is active.
Digital circuit ground terminals. These terminals should be tied together
to the low impedance circuit board ground plane.
Data I/Os. These are bi-directional data signals between the
PDI1394P21 and the LLC. Bus holders are built into these terminals.
Digital circuit power terminals. A combination of high frequency
decoupling capacitors near each terminal are suggested, such as
paralleled 0.1 µF and 0.001 µF. Lower frequency 10 µF filtering
capacitors are also recommended. These supply terminals are
separated from PLLVDD and AVDD internal to the device to provide
noise isolation. They should be tied at a low impedance point on the
circuit board.
Link interface isolation control input. This terminal controls the operation
of output differentiation logic on the CTL and D terminals. If an optional
isolation barrier of the type described in Annex J of IEEE Std 1394–1395
is implemented between the PDI1394P21 and LLC, the /ISO terminal
should be tied low to enable the differentiation logic. If no isolation barrier
is implemented (direct connection), or bus holder isolation is
implemented, the /ISO terminal should be tied high to disable the
differentiation logic.
Link Power Status input. This terminal is used to monitor the power
status of the LLC, and is connected to either the V_DD supplying the link
layer controller through a 1kΩ resistor, or to a pulsed output which is
active when the LLC is powered. The pulsed output is useful when using
an isolation barrier. If this input is low for more than 25 ms, the LLC is
considered powered down. If this input is high for more than 20 ns, the
LLC is considered powered up. If the LLC is powered-down, the
PHY–LLC interface is disabled, and the PDI1394P21 performs only the
basic repeater functions required for network initialization and operation.
Bus holder is built into this terminal.
LLC Request input. The LLC uses this input to initiate a service request
to the PDI1394P21. Bus holder is built into this terminal.
These pins are not internally connected, and consequently are “don’t
cares”. Other vendor’s pin compatible chips may require connections
and external circuitry on these pins.
Power Class programming inputs. On hardware reset, these inputs set
the default value of the power class indicated during self-ID.
Programming is done by tying the terminals high or low. Refer to
Table 18 for encoding.
Power Down input. A logic high on this terminal turns off all internal
circuitry except the cable-active monitor circuits which control the CNA
output. Bus holder is built into this terminal. For more information, refer to
Section 17.3
PLL circuit ground terminals. These terminals should be tied together to
the low impedance circuit board ground plane.
PLL circuit power terminals. A combination of high frequency decoupling
capacitors near each terminal are suggested, such as paralleled 0.1 µF
and 0.001 µF. Lower frequency 10 µF filtering capacitors are also
recommended. These supply terminals are separated from DVDD and
AVDD internal to the device to provide noise isolation. They should be
tied at a low impedance point on the circuit board.
1999 Jul 09
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