PDI1394P21 Datasheet, PDF (5/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
Name
/RESET
Pin Type
CMOS 5V tol
Pin Numbers
78
R0, R1
Bias
66, 67
SYSCLK
TEST0
TEST1
TPA0+,
TPA1+,
TPA2+
TPA0–,
TPA1–,
TPA2–
TPB0+,
TPB1+,
TPB2+
TPB0–,
TPB1–,
TPB2–
TPBIAS0,
TPBIAS1,
TPBIAS2
CMOS
CMOS
CMOS
Cable
Cable
Cable
Cable
Cable
2
33
32
45, 52, 58
44, 51, 57
43, 50, 56
42, 49, 55
46, 53, 59
XO, XI
Crystal
77, 76
I/O
Description
I
Logic reset input. Asserting this terminal low resets the internal logic. An
internal pull-up resistor to V_DD is provided so only an external
delay capacitor in parallel with a resistor is required for proper power-up
operation. For more information, refer to Section 17.3. This input is
otherwise a standard logic input, and can also be driven by an
open-drain type driver.
—
Current setting resistor terminals. These terminals are connected to
an external resistance to set the internal operating currents and
cable driver output currents. A resistance of 6.34 kΩ ±1% is required to
meet the IEEE Std 1394–1995 output voltage limits.
O
System clock output. Provides a 49.152 MHz clock signal, synchronized
with data transfers, to the LLC.
I
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
I
Test control input. This input is used in manufacturing tests of the
PDI1394P21. For normal use, this terminal should be tied to GND.
I/O
Twisted-pair cable A differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
I/O
matched and as short as possible to the external load resistors and to
the cable connector.
I/O
Twisted-pair cable B differential signal terminals. Board traces from each
pair of positive and negative differential signal terminals should be kept
I/O
matched and as short as possible to the external load resistors and to
the cable connector.
I/O
Twisted-pair bias output. This provides the 1.86V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and
receivers, and for signaling to the remote nodes that there is an active
cable connection. Each of these terminals must be decoupled with a
0.3 µF–1 µF capacitor to ground.
—
Crystal oscillator inputs. These terminals connect to a 24.576 MHz
parallel resonant fundamental mode crystal. The optimum values for the
external shunt capacitors are dependent on the specifications of the
crystal used. Can also be driven by an external clock generator (leave
XO unconnected in this case).
1999 Jul 09
5