PDI1394P21 Datasheet, PDF(25/28 Page) NXP Semiconductors

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PDI1394P21 Datasheet, PDF (25/28 Pages) NXP Semiconductors – 3-port physical layer interface

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Philips Semiconductors

3-port physical layer interface

Objective specification

PDI1394P21

18.4 Transmit

When the LLC issues a bus request through the LREQ terminal, the

PHY arbitrates to gain control of the bus. If the PHY wins arbitration

for the serial bus, the PHY-LLC interface bus is granted to the link by

asserting the Grant state (11b) on the CTL terminals for one

SYSCLK cycle, followed by Idle for one clock cycle. The LLC then

takes control of the bus by asserting either Idle (00b), Hold (01b), or

Transmit (10b) on the CTL terminals. Unless the LLC is immediately

releasing the interface, the link may assert the Idle state for at most

one clock before it must assert either Hold or Transmit on the CTL

terminals. The Hold state is used by the LLC to retain control of the

bus while it prepares data for transmission. The LLC may assert

Hold for zero or more clock cycles (i.e., the LLC need not assert

Hold before Transmit). The PHY asserts data-prefix on the serial

bus during this time.

When the LLC is ready to send data, the LLC asserts Transmit on

the CTL terminals as well as sending the first bits of packet data on

the D lines. The Transmit state is held on the CTL terminals until the

last bits of data have been sent. The LLC then asserts either Hold or

Idle on the CTL terminals for one clock cycle and then asserts Idle

for one additional cycle before releasing the interface bus and

putting the CTL and D terminals in a high-impedance state. The

PHY then regains control of the interface bus.

The Hold state asserted at the end of packet transmission indicates

to the PHY that the LLC requests to send another packet

(concatenated packet) without releasing the serial bus. The PHY

responds to this concatenation request by waiting the required

minimum packet separation time and then asserting Grant as

before. This function may be used to send a unified response after

sending an acknowledge, or to send consecutive isochronous

packets during a single isochronous period. Unless multi-speed

concatenation is enabled, all packets transmitted during a single bus

ownership must be of the same speed (since the speed of the

packet is set before the first packet). If multi-speed concatenation is

enabled (when the EMSC bit of PHY register 5 is set), the LLC must

specify the speed code of the next concatenated packet on the D

terminals when it asserts Hold on the CTL terminals at the end of a

packet. The encoding for this speed code is the same as the speed

code that precedes received packet data as given in Table 17.

After sending the last packet for the current bus ownership, the LLC

releases the bus by asserting Idle on the CTL terminals for two clock

cycles. The PHY begins asserting Idle on the CTL terminals one

clock after sampling Idle from the link. Note that whenever the D and

CTL terminals change direction between the PHY and the LLC,

there is an extra clock period allowed so that both sides of the

interface can operate on registered versions of the interface signals.

The sequence of events for a normal packet transmission is as

follows:

â¢ Transmit operation initiated. The PHY asserts grant on the CTL

lines followed by Idle to hand over control of the interface to the

link so that the link may transmit a packet. The PHY releases

control of the interface (i.e., it 3-States the CTL and D outputs)

following the idle cycle.

â¢ Optional idle cycle. The link may assert at most one idle cycle

preceding assertion of either hold or transmit. This idle cycle is

optional; the link is not required to assert Idle preceding either

hold or transmit.

â¢ Optional hold cycles. The link may assert hold for up to 47 cycles

preceding assertion of transmit. These hold cycle(s) are optional;

the link is not required to assert hold preceding transmit.

â¢ Transmit data. When data is ready to be transmitted, the link

asserts transmit on the CTL lines along with the data on the D

lines.

â¢ Transmit operation terminated. The transmit operation is

terminated by the link asserting hold or idle on the CTL lines the

link asserts hold to indicate that the PHY is to retain control of the

serial bus in order to transmit a concatenated packet. the link

asserts idle to indicate that packet transmission is complete and

the PHY may release the serial bus. The link then asserts Idle for

one more cycle following this cycle of hold or idle before releasing

the interface and returning control the the PHY.

â¢ Concatenated packet speed-code. If multi-speed concatenation is

enabled in the PHY, the link shall assert a speed-code on the D

lines when it asserts Hold to terminate packet transmission. This

speed-code indicates the transmission speed for the

concatenated packet that is to follow. The encoding for this

concatenated packet speed-code is the same as the encoding for

the received packet speed-code (see Table 17). the link may not

concatenate an S100 packet onto any higher speed packet.

â¢ After regaining control of the interface, the PHY shall assert at

least one cycle of idle before any subsequent status transfer,

receive operation, or transmit operation.

SYSCLK

CTL0, CTL1

(a)

(b)

(c)

(d)

D0âD7

d0, d1, ...

Link Controls Ctl and D

PHY High-impedance Ctl and D Outputs

NOTE: SPD = Speed code; see Table 17; d0âdn = Packet data.

Figure 14. Normal Packet Transmission Timing

(e)

(f)

SPD

(g)

SV01762

1999 Jul 09

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