PDI1394P21 Datasheet, PDF (7/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
data bits are split into two-, four- or eight-bit parallel streams
(depending upon the indicated receive speed), resynchronized to
the local 49.152 MHz system clock and sent to the associated LLC.
The received data is also transmitted (repeated) on the other active
(connected) cable ports.
Both the TPA and TPB cable interfaces incorporate differential
comparators to monitor the line states during initialization and
arbitration. The outputs of these comparators are used by the
internal logic to determine the arbitration status. The TPA channel
monitors the incoming cable common-mode voltage. The value of
this common-mode voltage is used during arbitration to set the
speed of the next packet transmission (speed signalling). In addition,
the TPB channel monitors the incoming cable common-mode
voltage on the TPB pair for the presence of the remotely supplied
twisted-pair bias voltage (cable bias detection).
The PDI1394P21 provides a 1.86 V nominal bias voltage at the
TPBIAS terminal for port termination. the PHY contains three
independent TPBIAS circuits. This bias voltage, when seen through
a cable by a remote receiver, indicates the presence of an active
connection. This bias voltage source must be stabilized by an
external filter capacitor of 0.3 µF–1 µF.
The line drivers in the PDI1394P21 operate in a high-impedance
current mode, and are designed to work with external 112 Ω
line-termination resistor networks in order to match the 110 Ω cable
impedance. One network is provided at each end of all twisted-pair
cable. Each network is composed of a pair of series-connected 56 Ω
resistors. The midpoint of the pair of resistors that is directly
connected to the twisted-pair A terminals is connected to its
corresponding TPBIAS voltage terminal. The midpoint of the pair of
resistors that is directly connected to the twisted-pair B terminals is
coupled to ground through a parallel R-C network with recommended
values of 5 kΩ and 220 pF. The values of the external line termination
resistors are designed to meet the standard specifications when
connected in parallel with the internal receiver circuits. An external
resistor connected between the R0 and R1 terminals sets the driver
output current, along with other internal operating currents. This
current setting resistor has a value of 6.34 kΩ ±1%.
When the power supply of the PDI1394P21 is removed while the
twisted-pair cables are connected, the PDI1394P21 transmitter and
receiver circuitry presents a high impedance to the cable in order to
not load the TPBIAS voltage on the other end of the cable.
When the PDI1394P21 is used with one or more of the ports not
brought out to a connector, the twisted-pair terminals of the unused
ports must be terminated for reliable operation. For each unused
port, the TPB+ and TPB– terminals can be tied together and then
pulled to ground, or the TPB+ and TPB– terminals can be connected
to the suggested termination network. The TPA+ and TPA– and
TPBIAS terminals of an unused port can be left unconnected.
The TEST0 and TEST1 terminals are used to set up various
manufacturing test conditions. For normal operation, the TEST0 and
TEST1 terminals should be connected to ground.
Four package terminals, used as inputs to set the default value for
four configuration status bits in the self-ID packet, should be
hard-wired high or low as a function of the equipment design. The
PC0–PC2 terminals are used to indicate the default power-class
status for the node (the need for power from the cable or the ability
to supply power to the cable). See Table 18 for power class
encoding. The C/LKON terminal is used as an input to indicate that
the node is a contender for bus manager.
The PHY supports suspend/resume as defined in the IEEE 1394a
specification. The suspend mechanism allows pairs of directly
connected ports to be placed into a low power state while
maintaining a port-to-port connection between 1394 bus segments.
While in a low power state, a port is unable to transmit or receive
data transaction packets. However, a port in a low power state is
capable of detecting connection status changes and detecting
incoming TPBIAS. When all three ports of the PDI1394P21 are
suspended, all circuits except the bias-detection circuits are
powered down, resulting in significant power savings. The TPBIAS
circuit monitors the value of incoming TPA pair common-mode
voltage when local TPBIAS is inactive. Because this circuit has an
internal current source and the connected node has a current sink,
the monitored value indicates the cable connection status. This
monitor is called connect-detect.
Both the cable bias-detect monitor and TPBIAS connect-detect
monitor are used in suspend/resume signaling and cable connection
detection. For additional details of suspend/resume operation, refer
to the 1394a specification. The use of suspend/resume is
recommended for new designs.
The port transmitter and receiver circuitry is disabled during power
down (when the PD input terminal is asserted high), during reset
(when the /RESET input terminal is asserted low), when no active
cable is connected to the port, or when controlled by the internal
arbitration logic. The port twisted-pair bias voltage circuitry is
disabled during power down, during reset, or when the port is
disabled as commanded by the LLC.
The CNA (cable-not-active) terminal provides a high output when all
twisted-pair cable ports are disconnected, and can be used along
with LPS to determine when to power down the PDI1394P21. The
CNA output is not debounced. In Power Down mode, the CNA
detection circuitry remains enabled.
The LPS (link power status) terminal works with the C/LKON
terminal to manage the power usage in the node. The LPS signal
from the LLC indicates to the PHY that the LLC is powered up and
active. During LLC Power Down mode, as indicated by the LPS
input being low for more than 25 µs, the PDI1394P21 deactivates
the PHY-LLC interface to save power. The PDI1394P21 continues
the necessary repeater function required for network operation
during this low power state.
If the PHY receives a link-on packet from another node, the C/LKON
terminal is activated to output a square-wave signal. The LLC
recognizes this signal, reactivates any powered-down portions of the
LLC, and notifies the PHY of its power-on status via the LPS
terminal. The PHY confirms notification by deactivating the
square-wave signal on the C/LKON terminal, then enables the
PHY-link interface.
1999 Jul 09
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