PDI1394P21 Datasheet, PDF(13/28 Page) NXP Semiconductors

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PDI1394P21 Datasheet, PDF (13/28 Pages) NXP Semiconductors – 3-port physical layer interface

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Philips Semiconductors

3-port physical layer interface

Objective specification

PDI1394P21

FIELD

Pwr_Class

RPIE

ISBR

CTOI

CPSI

STOI

PEI

EAA

EMC

Page_Select

Port_Select

SIZE

TYPE

Rd/Wr

DESCRIPTION

Node power class. This field indicates this nodeâs power consumption and source characteristics and is

replicated in the pwr field (bits 21â23) of the self-ID packet. This field is reset to the state specified by

the PC0âPC2 input terminals upon hardware reset, and is unaffected by a bus reset. See Table 18.

Resuming port interrupt enable. This bit, if set to 1, enables the port event interrupt (PEI) bit to be set

whenever resume operations begin on any port. This bit is reset to 0 by hardware reset and is

unaffected by bus reset.

Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY to initiate a short (1.3 Âµs)

arbitrated bus reset at the next opportunity. This bit is reset to 0 by a bus reset.

NOTE: Legacy IEEE Std 1394â1995 compliant PHYs are not capable of performing short bus resets.

Therefore, initiation of a short bus reset in a network that contains such a legacy device results in a long

bus reset being performed.

Configuration time-out interrupt. This bit is set to 1 when the arbitration controller times-out during

tree-ID start, and may indicate that the bus is configured in a loop. This bit is reset to 0 by hardware

reset, or by writing a 1 to this register bit.

NOTE: If the network is configured in a loop, only those nodes which are part of the loop should

generate a configuration time out interrupt. All other nodes should instead time out waiting for the

tree-ID and/or self-ID process to complete and then generate a state time-out interrupt and bus-reset.

Cable-power-status interrupt. This bit is set to 1 whenever the CPS input transitions from high to low

indicating that cable power may be too low for reliable operation. This bit is reset to 0 by hardware

reset, or by writing a 1 to this register bit.

State time-out interrupt. This bit indicates that a state time-out has occurred. This bit is reset to 0 by

hardware reset, or by writing a 1 to this register bit.

Port event interrupt. This bit is set to 1 on any change in the connected, bias, disabled, or fault bits for

any port for which the port interrupt enable (PIE) bit is set. Additionally, if the resuming port interrupt

enable (RPIE) bit is set, the PEI bit is set to 1 at the start of resume operations on any port. This bit is

reset to 0 by hardware reset, or by writing a 1 to this register bit.

Enable arbitration acceleration. This bit enables the PHY to perform the various arbitration acceleration

enhancements defined in P1394a (ACK-accelerated arbitration, asynchronous fly-by concatenation,

and isochronous fly-by concatenation). This bit is reset to 0 by hardware reset and is unaffected by bus

reset.

NOTE: The EAA bit should be set only if the attached LLC is P1394a compliant. If the LLC is not

P1394a compliant, use of the arbitration acceleration enhancements can interfere with isochronous

traffic by excessively delaying the transmission of cycle-start packets.

Enable multispeed concatenated packets. This bit enables the PHY to transmit concatenated packets of

differing speeds in accordance with the protocols defined in P1394a. This bit is reset to 0 by hardware

reset and is unaffected by bus reset.

NOTE: The use of multispeed concatenation is completely compatible with networks containing legacy

IEEE Std 1394â1995 PHYs. However, use of multispeed concatenation requires that the attached LLC

be P1394a compliant.

Page_Select. This field selects the register page to use when accessing register addresses 8 through

15. This field is reset to 0 by a hardware reset and is unaffected by bus-reset.

Port_Select. This field selects the port when accessing per-port status or control (e.g., when one of the

port status/control registers is accessed in page 0). Ports are numbered starting at 0. This field is reset

to 0 by hardware reset and is unaffected by bus reset.

1999 Jul 09

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