PDI1394P21 Datasheet, PDF (26/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
The sequence of events for a cancelled/null packet transmission is
as follows:
• Transmit operation initiated. PHY asserts grant on the CTL lines
followed by idle to hand over control of the interface to the link.
• Optional Idle cycle. The link may assert at most one idle cycle
preceding assertion of hold. This idle cycle is optional; the link is
not required to assert idle preceding Hold.
• Optional Hold cycles. The link may assert Hold for up to 47 cycles
preceding assertion of idle. These hold cycle(s) are optional; the
link is not required to assert hold preceding Idle.
• Null transmit termination. The null transmit operation is terminated
by the link asserting two cycles of idle on the CTL lines and then
releasing the interface and returning control to the PHY. Note that
the link may assert Idle for a total of 3 consecutive cycles if it
asserts the optional first idle cycle but does not assert hold. It is
recommended that the link assert 3 cycles of Idle to cancel a
packet transmission if no hold cycles are asserted. This ensures
that either the link or PHY controls the interface in all cycles.
• After regaining control of the interface, the PHY shall assert at
least one cycle of Idle before any subsequent status transfer,
receive operation, or transmit operation.
SYSCLK
(a)
(b)
(c)
CTL0, CTL1
00
11
00
00
01
(d)
(e)
00
00
D0–D7
00
00
Link Controls Ctl and D
PHY High-impedance Ctl and D Outputs
Figure 15. Cancelled/Null Packet Transmission
00
SV01763
19.0 POWER-CLASS PROGRAMMING
The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted
self-ID packet. Descriptions of the various power-classes are given in Table 18. The default power-class value is loaded following a hardware
reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4.
Table 18. Power Class Descriptions
PC0–PC2
DESCRIPTION
000
Node does not need power and does not repeat power.
001
Node is self powered, and provides a minimum of 15 W to the bus.
010
Node is self powered, and provides a minimum of 30 W to the bus.
011
Node is self powered, and provides a minimum of 45 W to the bus.
100
Node may be powered from the bus and is using up to 3 W.
101
Node is powered from the bus and uses up to 3 W. No additional power is needed to enable the link.
110
Node is powered from the bus and uses up to 3 W. An additional 3 W is needed to enable the link.
111
Node is powered from the bus and uses up to 3 W. An additional 7 W is needed to enable the link.
1999 Jul 09
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