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PDI1394P21 Datasheet, PDF (17/28 Pages) NXP Semiconductors – 3-port physical layer interface
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Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
17.1 External Component Connections
VDD
12 pF
12 pF
24.576 MHz
0.1 µF
6.34 kΩ
±1%
0.1 µF
0.001 µF
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1 LREQ
2 SYSCLK
3 DGND
4 CTL0
5 CTL1
6 DVDD
7 D0
8 D1
9 NC
10 D2
11 D3
12 D4
13 D5
14 D6
15 D7
16 DGND
CNA OUT 17 CNA
POWER DOWN 18 PD
LINK PULSE
OR VDD
19
LPS
20 DGND
REFER TO
FIGURE 7
PDI1394P21
AGND 60
TPBIAS2 59
TPA2+ 58
TPA2– 57
TPB2+ 56
TPB2– 55
AVDD 54
TPBIAS1 53
TPA1+ 52
TPA1– 51
TPB1+ 50
TPB1– 49
AVDD 48
AVDD 47
TPBIAS0 46
TPA0+ 45
TPA0– 44
TPB0+ 43
TPB0– 42
AGND 41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE
CONNECTION
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE
CONNECTION
0.3–1.0 µF
TPBIAS
TP CABLES
INTERFACE
CONNECTION
10 kΩ
370–
410 kΩ
See Figure 6 for recommended power and ground connections.
Figure 8. External Component Connections
SV001756
1999 Jul 09
17
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