PDI1394P21 Datasheet, PDF (18/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
17.2 Using the PDI1394P21 with a non-P1394a
link layer
The PDI1394P21 implements the PHY-LLC interface specified in the
P1394a Supplement. This interface is based upon the interface
described in informative Annex J of IEEE Std 1394-1995, which is the
interface used in older PHY devices. The PHY-LLC interface specified
in P1394a is completely compatible with the older Annex J interface.
The P1394a Supplement includes enhancements to the Annex J
interface that must be comprehended when using the PDI1394P21
with a non-P1394a LLC device.
• A new LLC service request was added which allows the LLC to
temporarily enable and disable asynchronous arbitration
accelerations. If the LLC does not implement this new service
request, the arbitration enhancements should not be enabled (see
the EAA bit in PHY register 5).
• The capability to perform multispeed concatenation (the
concatenation of packets of differing speeds) was added in order
to improve bus efficiency (primarily during isochronous
transmission). If the LLC does not support multispeed
concatenation, multispeed concatenation should not be enabled in
the PHY (see the EMC bit in PHY register 5).
• In order to accommodate the higher transmission speeds expected
in future revisions of the standard, P1394a extended the speed
code in bus requests from 2 bits to 3 bits, increasing the length of
the bus request from 7 bits to 8 bits. The new speed codes were
carefully selected so that new P1394a PHY and LLC devices would
be compatible, for speeds from S100 to S400, with legacy PHY and
LLC devices that use the 2-bit speed codes. The PDI1394P21
correctly interprets both 7-bit bus requests (with 2-bit speed code)
and 8-bit bus requests (with 3-bit speed codes). Moreover, if a 7-bit
bus request is immediately followed by another request (e.g., a
register read or write request), the PDI1394P21 correctly interprets
both requests. Although the PDI1394P21 correctly interprets 8-bit
bus requests, a request with a speed code exceeding S400 results
in the PDI1394P21 transmitting a null packet (data-prefix followed
by data-end, with no data in the packet).
17.3 /Reset and Power Down
Forcing the /RESET pin low causes a Bus Reset condition on the
active cable ports, and resets the internal logic to the Reset Start
state. SYSCLK remains active. For power-up (and after Power
Down is asserted) /RESET must be asserted low for a minimum of
2 ms from the time that the PHY power reaches the minimum
required supply voltage. This is required to assure proper PLL
operation before the PHY begins using the clock. An internal pull-up
resistor is connected to V_DD, so only an external delay capacitor is
required. When using a passive capacitor on the /RESET terminal to
generate a power-on reset signal, the minimum value of 0.1 µF and
also satisfies the following equation:
C_min = 0.0077 × T + 0.085
where C_min is the minimum capacitance on the /RESET terminal in
µF, and T is the V_DD ramp time, 10%–90%, in ms.
Additionally, an approximately 120 kΩ resistor should be connected
in parallel with the reset capacitor from the /RESET terminal to GND
to ensure that the capacitor is discharged when PHY power is
removed. An alternative to the passive reset is to actively drive
/RESET low for the minimum reset time following power on. This
input is a standard logic buffer and may also be driven by an open
drain logic output buffer.
The /RESET pin also has a n-channel pull-down transistor activated
by the Power Down pin. For a reset during normal operation, a 10 us
low pulse on this pin will accomplish a full PHY reset. This pulse, as
well as the 2 ms power up pulse, could be microprocessor
controlled, in which case the external delay capacitor would not be
needed. For more details on using single capacitor isolation with this
pin, please refer to the Philips Isolation Application Note AN2452
The Power Down input powers down all device functions with the
exception of the CNA circuit to conserve power in portable or
battery-powered applications. It must be held high for at least 3.5 ms
to assure a successful reset after power down. This pin is equipped
with Bus Hold circuitry and supports an optional isolation barrier.
1999 Jul 09
18