PDI1394P21 Datasheet, PDF (6/28 Pages) NXP Semiconductors – 3-port physical layer interface

Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P21
6.0 BLOCK DIAGRAM
CPS
LPS
/ISO
C/LKON
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
CNA
LINK
INTERFACE
I/O
R0
R1
TPBIAS0
TPBIAS1
TPBIAS2
PD
/RESET
RECEIVED DATA
DECODER/
RETIMER
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
BIAS VOLTAGE
AND
CURRENT
GENERATOR
TRANSMIT
DATA
ENCODER
CABLE POWER
DETECTOR
CPS
CABLE PORT 0
TPA0+
TPA0–
TPB0+
TPB0–
CABLE PORT 1
CABLE PORT 2
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
TPA1+
TPA1–
TPB1+
TPB1–
TPA2+
TPA2–
TPB2+
TPB2–
XI
XO
SV01743
7.0 FUNCTIONAL SPECIFICATION
The PDI1394P21 requires only an external 24.576 MHz crystal as a
reference. An external clock can be provided instead of a crystal. An
internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216 MHz reference signal. This
reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.
The PDI1394P21 supports an optional isolation barrier between
itself and its LLC. When the /ISO input terminal is tied high, the
LLC interface outputs behave normally. When the /ISO terminal is
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in IEEE 1394a
section 5.9.4. To operate with single capacitor (bus holder) isolation,
the /ISO on the PHY terminal must be tied high.
Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P21 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at
98.304/196.608/392.216 Mbits/s (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TPA cable
pair(s).
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
1999 Jul 09
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