PDI1394L41 Datasheet, PDF (77/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
16.4 Host Interface Critical Timings
READ
t_AS
t_AS
HIF A[7:0]
VALID
t_CL
HIF CS_N
t_RP
HIF RD_N
HIF D[7:0]
t_AS ^{ÉÉÉÉÉÉÉÉÉÉÉÉ}_tA^ÉÉÉ_CC ^{ÉÉÉÉÉÉÉÉÉÉÉÉ}
A8
WAIT
t_WAIT
t_PWWAIT
t_AH
t_AH
t_CH
VALID
t_DZ
WRITE
HIF WR_N
t_WRP
HIF D[7:0]
t_DS
A8
VALID
WAIT
t_WAIT
Note: Wait line asserts only during Read and Write cycles in which A8 is asserted.
Figure 40. Host Interface Timing Waveforms
16.5 CYCLEIN/CYCLEOUT Timings
CYCLEIN
50%
50%
50%
t_CWH
t_CWL
t_CP
Figure 41. CYCLEIN Waveform
t_DH
SV00696
2000 Apr 15
74
SV01776