PDI1394L41 Datasheet, PDF (64/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
13.3 Asynchronous Control and Status Interface
13.3.1 Asynchronous RX/TX Control (ASYCTL) – Base Address: 0x080
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAXRC TOS
TOF
SV00889
Reset Value 0x00300320
Bit 23:
R/W DIS_BCAST: Disable the reception of broadcast packets (async packets address to 0x3F).
Bit 22:
R/W ARXRST: Asynchronous receiver reset. This bit will auto clear when the link layer state machine is idle.
Bit 21:
R/W ATXRST: Asynchronous transmitter reset. the power-up reset value of this bit is “0”, however, after every bus reset
this bit is set (1). this effectively disables the asynchronous transmitter; re-enable the async transmitter by clearing
this bit after each bus reset, especially if asynchronous transmission is to be used.
Bit 20:
R/W ARXALL: Receive and filter only RESPONSE packets. When set (1), all responses are stored. When clear (0), only
solicited responses are stored.
Bit 19..16:
R/W MAXRC: Maximum number of asynchronous transmitter single phase retries
Bit 15..13:
R/W TOS: Time out seconds, integer of 1 second
Bit 12..0:
R/W TOF: Time out fractions, integer of 1/8000 second. Resets to 0320h, which is 100 milliseconds.
13.3.2 Asynchronous RX/TX Memory Status (ASYMEM) – Base Address: 0x084
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00918
Reset Value 0x00033333
Unused bits read ‘0’. The information in this register is primarily used for diagnostics.
Bit 17:
R
TRSPQIDLE: Transmitter response queue is idle. Indicates that the transfer register for this queue is empty.
Bit 16:
R
TREQQIDLE: Transmitter request queue is idle. Indicates that the transfer register for this queue is empty.
Bit 15:
R
RRSPQF: Receiver response queue full.
Bit 14:
R
RRSPQAF: Receiver response queue almost full (precisely 1 more quadlet available).
Bit 13:
R
RRSPQ5AV: Receiver response queue at least 5 quadlets available.
Bit 12:
R
RRSPQE: Receiver response queue empty.
Bit 11:
R
RREQQF: Receiver request queue full.
Bit 10:
R
RREQQAF: Receiver request queue almost full (precisely 1 more quadlet available).
Bit 9:
R
RREQQ5AV: Receiver request queue at least 5 quadlets available.
Bit 8:
R
RREQQE: Receiver request queue empty.
Bit 7:
R
TRSPQF: Transmitter response queue full.
Bit 6:
R
TRSPQAF: Transmitter response queue almost full (precisely 1 more quadlet available).
Bit 5:
R
TRSPQ5AV: Transmitter response queue at least 5 quadlets available.
Bit 4:
R
TRSPQE: Transmitter response queue empty.
Bit 3:
R
TREQQF: Transmitter request queue full.
Bit 2:
R
TREQQAF: Transmitter request queue almost full (precisely 1 more quadlet available).
Bit 1:
R
TREQQ5AV: Transmitter request queue at least 5 quadlets available.
Bit 0:
R
TREQQE: Transmitter request queue empty.
2000 Apr 15
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