PDI1394L41 Datasheet, PDF (58/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
13.2.6 Isochronous Transmitter Control Register (ITXCTL) – Base Address: 0x34
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TAG CHANNEL
SPD EMI
SV01016
Reset Value 0x00000000
Bit 20:
R/W Cipher Enable: When set, the internal M6 cipher will encrypt the application packets with the associated key in the
M6 indirect address space for the given EMI value assigned. When the EMI value changes the cipher will
automatically change the key on the next application packet. Writes to the ODD/EVEN bit (bit 1 will automatically
swap the odd/even key in the cipher. Note: the maximum average data rate for the M6 cipher is 60 Mbps.
Bit 15..14:
R/W Tag: Tag code to insert in isochronous bus packet header. Should be ‘01’ for IEC 61883 International Standard data.
Bit 13..8:
R/W Channel: Isochronous channel number.
Bit 5..4:
R/W Speed: Cable transmission speed (S100, S200, S400).
00 = 100Mbs
01 = 200Mbs
10 = 400Mbs
11 = reserved
Bit 3..2
R/W Encryption Mode Indication: This bit pattern specifies the level of copy control information for the data stream. The
field only has significance when the internal cipher is enabled (CPHR_EN = 1). The bits are read only and follow the
value of the AVxEMI pins when EMI_PE = 1 (bit 19). The bits are read/write when EMI_PE = 0. See the “5C Digital
Transmission Content Protections Specification, Volume 1” for more details about EMI values.
Bit 1
R/W Odd even bit used for encryption key (0 = even, 1 = odd). When the internal M6 cipher is enabled (CPHR_EN = 1), a
write that changes this bit field will cause the cipher to swap its odd/even key. The key will be changed on the very
next application packet and an interrupt (ODDEVN) will be generated. See the “5C Digital Transmission Content
Protection Specification, Volume 1” for more details about odd/even values. When the internal cipher is not enabled
(CPHR_EN = 0) the bit value is R/W and the current bit value will be transmitted in the isochronous header.
Bit 0
R
SY: Sync code to insert in SY field of isochronous bus packet header. This bit reflects the value of the AVx SY pin
and is synchronized with the data payload that was associated with it.
13.2.7 Isochronous Transmitter Memory Status (ITXMEM) – Base Address: 0x038
The AV Transmitter Memory Status register reports on the condition of the internal memory buffer used to store incoming AV data streams
before transmission over the 1394 bus. This register is used primarily for diagnostics; several memory status flags are also available in the
ITXINTACK register.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01056
Reset Value 0x00000003
BIT 6:
R
ITXM100LFT: 100 or less quadlets of storage available.
Bit 5:
R
ITXM256LFT: Memory has 256 quadlets of space remaining before becoming full.
Bit 4:
R
ITXM512LFT: Memory has 512 quadlets of space remaining before becoming full.
Bit 3:
R
ITXMF: memory is completely full, no storage available.
Bit 2:
R
ITXMAF: almost full, exactly one quadlet of storage available.
Bit 1:
R
ITXM5AV: at least 5 more quadlets of storage available.
Bit 0:
R
ITXME: memory bank is empty (zero quadlets stored).
2000 Apr 15
55