PDI1394L41 Datasheet, PDF (16/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
12.3.2 Single capacitor isolation
The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation.
NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits
provide local dc ground references to each side of the isolating/coupling capacitors. Also note that ground isolation/signal-coupling must be
provided in the form of a parallel combination of resistance and capacitance as indicated in the IEEE 1394 standard.
APPLICATION/LINK
+3.3V
ISOLATED/PHY
+3.3V
ISON
LINK
SCLK
PDI1394L41 PHY D0
PHY D1
PHY D2
PHY D3
PHY D4
PHY D5
PHY D6
PHY D7
PHYCTL0
PHYCTL1
LREQ
LPS
APPLICATION AND LINK GROUND
LINKON
C_c
C_c
C_c
C_c
LINK
3.3V
C_c
C_c
C_c
C_c
C_c
C_c
C_c
C_c
C_L
C_L
PHY
3.3V
ISO–
SYSCLK
PHY
D0
PDI1394P2x
D1
D2
D3
D4
D5
D6
D7
PHYCTL0
PHYCTL1
LREQ
LPS
LINKON
ISOLATED PHY GROUND
ALSO SEE APPLICATION NOTE AN2452
FOR MORE DETAILS
13K
9.1K
C_c
1MEG Ω
C_r
VALUES OF THESE RESISTORS DEPEND
ON PHY USED. SEE PHY DATASHEET.
C_C = 1 nF; C_r = 100 nF; C_L = 3.3nF
SV01816
Figure 3. Single capacitor Link/PHY isolation
12.4 Power Management
The PDI1394L41 implements several features for power management as noted in the P1394a draft 5.0. These features include:
1. Reset of the Phy/Link interface by setting the RPL bit in the LNKCTL register.
2. Disable of the Phy/Link interface caused by either setting the SWPD bit in the RDI register –OR– asserting (high) the PD pin.
3. Initialization of the Phy/Link interface after it was disabled or reset.
The application can power up the Phy/Link interface by deasserting the PD pin –OR– clearing (low) the SWPD in the RDI register. This will
cause the L41 to produce a pulsing signal on the LPS pin. When the L41 is in power down mode, reads and writes to the host interface will be
restricted to those addressing only the RDI register (0x0B0). Please see Section 13.3.11 for further details.
There are 3 ways to power up the L41. (1) When the application wants the 1394 node to resume operation, it simply needs to de–assert the PD
pin, or (2) clear the SWPD bit in the RDI register. The link can also be awakened by another bus node sending a link–on packet to the PHY of
the application’s node. (3) The attached PHY will activate its LinkOn line and the L41 will see the signal and set the LOA bit of the RDI register
(assuming that the ELOA bit is in its enabled, ”1”, state). The L41 will generate an interrupt of the host processor. It will then be up to the host
processor to decide whether to honor the link–on request of the other node. Then the host processor will de–assert the PD pin –OR– clear the
SWPD bit in the RDI register. This activity will power up the L41 causing it to send the pulsing signal out on the LPS pin which notifies the
PHYchip of link activity and allows the PHY to discontinue directing the link on signal to the L41. Subsequently, the host processor must
acknowledge the LOA interrupt by writing a ”1” to the LOA bit position in the RDI register after the link on signal from the PHY has stopped.
2000 Apr 15
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