PDI1394L41 Datasheet, PDF (18/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
12.5.2 Write accesses
To write to an internal register the host interface must collect the 4 byte values (8 bit mode) or 2 word values (16 bit mode) into a 32 bit value
and then write the result to the target register in a single clock tick. This requires a register to hold the 32 bit value being compiled until it is
ready to be written to the actual target register. This temporary register inside the host interface is called the shadow register. In 8 bit mode,
address lines HIF A0 and HIF A1 are used to select which of the 4 bytes of the shadow register is to be written with the value on the CPU data
bus. In 16 bit mode, HIF A1 is used to select which half of the shadow register is to be written with the value on the CPU data bus. Only one
byte (8 bit mode) or one word (16 bit mode) can be written in a single write access cycle.
Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the
FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly
addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).
MUX
TR
MUX
Q
8/16
32
CPU
Q
HIF A0..1 (8 BIT MODE)
HIF A1 (16 BIT MODE)
HIF A2..7
HIF A8
UPDATE/COPY CONTROL
REGISTERS
32
SV01035
NOTES:
1. It is not required to write all 4 bytes, or both words of a register: those bytes that are either reserved (undefined) or don’t care do not have
to be written in which case they will be assigned the value that was left in the corresponding byte of the shadow register from a previous
write access. For example, to acknowledge an interrupt for the isochronous receiver in 8 bit mode, a single byte write to location
0x100+(0x4C)+3 = 0x14F is sufficient. The value 256 represents setting HIF A8=1. The host interface cannot directly access the FIFOs, but
instead reads from/writes into a transfer register (shown as TR in the Figures above). Data is moved between FIFO and TR by internal logic
as soon as possible without CPU intervention.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byte 3 or the
upper 16 bits. This makes the internal updating automatic for quadlet writing.
3. Writing the bytes or words of the shadow register can be done in any order and as often as needed (new writes simply overwrite the old
value).
4. It is now possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an
enable bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of
the modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.
2000 Apr 15
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