PDI1394L41 Datasheet, PDF (43/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
12.6.2.13 Link data confirmation formats
After a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a Link data confirmation (see
Figure 32) which is used to confirm the transmission to the higher layers. Packets transmitted from the Transmit Request FIFO are confirmed by
a confirmation written into the Receive Request FIFO and packets transmitted from the Transmit Response FIFO are confirmed by a
confirmation written into the Receive Response FIFO.
Outgoing packets and their confirmations are associated by their tLabels. It is the user’s responsibility to assure the uniqueness of active
tLabels.
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tLabel
01 1000
conf
SV01051
Figure 32. Request and response confirmation format
Table 5. Confirmation codes
CODE¹
DESCRIPTION
0
Non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete).
1
Broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete
(transaction complete).
2
Non-broadcast packet transmitted; addressed node returned an acknowledge pending.
4
Retry limit exceeded; destination node hasn’t accepted the non-broadcast packet within the maximum number of retries
(transaction complete).
D₁₆
Acknowledge data error received (transaction complete).
E₁₆
Acknowledge type error received (transaction complete).
NOTE:
1. All other codes are reserved.
12.7 Interrupts
The PDI1394L41 provides a single interrupt line (HIF INTN) for connection to a host controller. Status indications from four major areas of the
device are collected and ORed together to activate HIF INTN. Status from four major areas of the device are collected in four status registers;
LNKPHYINTACK, ITXINTACK, IRXINTACK, and ASYINTACK. At this level, each individual status can be enabled to generate a chip-level
interrupt by activating HIF INTN. To aid in determining the source of a chip-level interrupt, the major area of the device generating an interrupt is
indicated in the lower 4 bits of the GLOBCSR register. These bits are non-latching Read-Only status bits and do not need to be acknowledged.
To acknowledge and clear a standing interrupt, the bit in LNKPHYINTACK, ITXINTACK, IRXINTACK, or ASYINTACK causing the interrupt
status has to be written to a logic ‘1’; Note: Writing a value of ‘0’ to the bit has no effect.
12.7.1 Determining and Clearing Interrupts
When responding to an interrupt event generated by the PDI1394L41, or operating in polled mode, the first register examined is the GLOBCSR
register. The least significant nibble contains interrupt status bits from general sections of the device; the link layer controller, the AV transmitter,
the AV receiver, and the asynchronous transceiver. The bits in GLOBCSR[3:0] are self clearing status bits. They represent the logical OR of all
the enabled interrupt status bits in their section of the AV Link Layer Controller.
Once an interrupt, or status is detected in GLOBCSR, the appropriate interrupt status register needs to be read, see the Interrupt Hierarchy
diagram for more detail. After all the interrupt indications are dealt with in the appropriate interrupt status register, the interrupt status indication
will automatically clear in the GLOBCSR.
All interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
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