PDI1394L41 Datasheet, PDF (68/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R/W PLI: PHY – link interface initialized interrupt. This interrupt indicates when the PHY – link initialization routine has
been accomplished. This bit will be set upon completion of the initialization; if enabled, it will cause a host interface
interrupt in order to inform the host controller of the completed action. Reset of this interrupt requires the writing of a
(1) to this bit position.
R/W LOA: Link–on active interrupt. This interrupt will become active when a link–on signal is received by the link from the
PHY. This bit will remain active as long as the link–on signal is active. When enabled, this bit will set and cause a
host interface interrupt when the link detects the presence of a link–on signal from the PHY. In practice, the link will
be in the power down state when this interrupt occurs (a link–on packet was sent by another node on the bus which
desires to communicate with this powered down node). Proper servicing of this interrupt will contain a scenario
similar to: this node is in power down mode and the host controller has set the ELOA bit to enable the interrupt and
the PHY of this node received a link–on packet from another node requesting this node to power up; (1) the host
controller gets the interrupt and makes a decision to power up, (2) the host de–asserts SWPD (by hardware or
software means... see SWPD above), (3) the host monitors SCA for a ”1” state, (4) when SCA is true, the host writes
a 0 to the ELOA bit and then writes a 1 to the LOA interrupt bit to cancel the interrupt. The link is now powered up.
R/W SCA: SCLK active interrupt. When the SCLK signal from the PHY to the link is present, this bit is set. If this interrupt
has been enabled, the host will receive an interrupt when the SCLK becomes active (an example of such use might
be during the recovery from a link power down situation).
R/W SCI: SCLK inactive interrupt. When the SCLK signal is NOT active, this bit sets. If this interrupt is enabled, when the
SCLK ceases to be active, the interrupt will occur. SCLK could become inactive due to the PHY connected to this
link going into power down mode.
13.3.12 Shadow Register (SHADOW_REG) – Base Address: 0x0F4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 0
BYTE 1
BYTE 2
BYTE 3
SV01817
Reset Value 0x0F0A0500
Bit 31..0:
R/W The shadow register is a mechanism that allows a byte (8-bit) or word (16-bit) host interface write quadlets (32-bit)
into the AV Link. Bytes or words can be written into the shadow register in any order and then written to the AV Link
by asserting address line A8 with the desired address. For example, if you want to write to Transmit Request Next
register (TX_RQ_NEXT), and you were using an 8-bit host, then you would write the first three bytes to the shadow
register and the fourth byte to the address 0x188 (or 0x189, or 0x18A, or 0x18B). In practice, any write or read with
address line A8 not asserted will be directed to the shadow register. To verify the settings of LTLEND and DATAINV,
this register is initialized to 0x0F0A0500 on power up. Note, unlike the other registers in this device, access to this
register should not be addressed with address line A8 = 1.
2000 Apr 15
65