PDI1394L41 Datasheet, PDF (66/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
13.3.7 Asynchronous Receive Request (RREQ) – Base Address: 0x098
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
SV00297
Reset Value 0x00000000
Bit 31..0:
R
RREQ:Quadlet of packet from receiver request queue (transfer register).
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
13.3.8 Asynchronous Receive Response (RRSP) – Base Address: 0x09C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
SV00298
Reset Value 0x00000000
Bit 31..0:
R
RRSP:Quadlet of packet from receiver response queue (transfer register).
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
13.3.9 Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV00796
Reset Value 0x00000C00
Bit 31..17:
R/W Unused bits read ‘0’
Bit 16:
R/W RRSPQFULL: Receiver response queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 15:
R/W RREQQFULL: Receiver request queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 14:
R/W SIDQAV: Current quadlet in RREQ is selfID data. This bit is set only after a bus reset, not after reception of PHY
packets other than self IDs. This interrupt automatically resets when the quadlet is read.
Bit 13:
R/W RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
Bit 12:
R/W RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
Bit 11:
R/W RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
Bit 10:
R/W RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
Bit 9:
R/W RRSPQQAV: Receiver response queue quadlet available (in RRSP). This interrupt automatically resets when the
quadlet is read.
Bit 8:
R/W RREQQQAV: Receiver request queue quadlet available (in RREQ). This interrupt automatically resets when the
quadlet is read.
Bit 7:
R/W TIMEOUT: Split transaction response timeout. Write a “1” to this bit to reset the interrupt.
Bit 6:
R/W RCVDRSP: Solicited response received (within timeout interval). Write a “1” to this bit to reset the interrupt.
Bit 5:
R/W TRSPQFULL: Transmitter response queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 4:
R/W TREQQFULL: Transmitter request queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 3:
R/W TRSPQWRERR: Transmitter response queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
Bit 2:
R/W TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
Bit 1:
R/W TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
Bit 0:
R/W TREQQWR: Transmitter request queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
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