PDI1394L41 Datasheet, PDF (74/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
15.0 AC CHARACTERISTICS
GND = 0V, C_L = 50pF
SYMBOL
PARAMETER
TEST CONDITIONS
t_PERIOD
(parallel
mode)
t_SU
t_IH
t_OD
t_WHIGH
t_WLOW
t_PWFS
t_SUP
t_HP
t_SCLKPER
t_DP
t_AS
t_AH
t_CL
t_CH
t_RP
t_ACC
t_DH
t_DS
t_DZ
t_WRP
t_WAIT
t_WWAIT
t_CWH
t_CWL
t_CP
t_CD
t_RESET
t_PWALE
AV clock period
AV clock setup time
AV clock input hold time
AV clock output delay time
AV clock pulse width HIGH
AV clock pulse width LOW
AVxFSYNC pulse width HIGH
PHY-link setup time
PHY-link hold time
SCLK period
PHY-link output delay
Host address setup time
Host address hold time
Host chip select pulse width LOW
Host chip select pulse width HIGH
Host read pulse width
Host access time
Host data hold time
Host data setup time
Host data bus release (Hi-Z)
Host write pulse width
WAIT output delay
WAIT pulse width
CYCLEIN HIGH pulse width
CYCLEIN LOW pulse width
CYCLEIN cycle period
CYCLEOUT cycle delay
RESET_N pulse width LOW
ALE pulse width
Note: C_L = 20pF
WAVEFORMS
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 37
Figure 38
Figure 38
Figure 38
Figure 39
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 40
Figure 41
Figure 41
Figure 41
Figure 42
Figure 43
Figures 7, 8, 9, 10
LIMITS
T_amb = 0°C to +70°C
MIN
TYP MAX
UNIT
41.67
ns
20
ns
3
ns
3
24
ns
10
10
200
300
ns
6.0
ns
0
ns
20.343 20.345 20.347 ns
2.0
10.0
ns
0
ns
0
ns
115
ns
42
ns
115
ns
115
ns
0
ns
0
ns
15
ns
115
ns
10
ns
20
ns
200
ns
200
ns
125
µs
20
ns
10
µs
20
ns
2000 Apr 15
71