PDI1394L41 Datasheet, PDF (67/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
13.3.10 Asynchronous RX/TX Interrupt Enable (ASYINTE) – Base Address: 0x0A4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset Value 0x00000000
Bits16..0 are interrupt enable bits for the Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK).
13.3.11 RDI Register – Base Address: 0x0B0
SV00797
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SV01779
Reset Value 0x00000000
Note: Before asserting the RPL bit, SWPD or setting the PD pin high, the user should assure that the link chip is in
the following state of operation:
1) The isochronous transmit FIFO is not receiving data for transmission
2) The isochronous transmitter is disabled
3) No asynchronous packets are being generated for transmission
4) Both the ASYNC request and response queues are empty
Bit 31:
R/W SWPD: Software power–down. Writing a 1 to this register bit will cause the link to de–activate its LPS pin causing the
PHY to turn off the SCLK to the link. This, in turn, causes the link chip to go into a low power mode in which only the
RDI register is accessible. The function of this bit is identical to that of the hardware pin ”PD”. When PD is set (1),
SWPD will be set automatically by the pin state and will cause entry into the power down mode as stated above. DO
NOT USE BOTH (HARDWARE AND SOFTWARE) MODES OF OPERATION TO CAUSE THE POWER DOWN
FUNCTION. Use either hardware mode (the PD pin) OR the software method (setting / resetting the SWPD bit), not
both. The PD pin will take precedence over the software method... the link will not come out of PD mode unless the
PD pin is de–asserted (0). An unused PD pin should be connected to the link chip ground.
Bit 30:
R
LPSTAT: Link – PHY interface status. This bit reflects the status of the LPS signal. When the LPS signal is active
(pulsing) the PHY interprets it as indicating that the link power is on and the link is requesting to be activated. The
PHY, in turn, supplies the SCLK to the link, thus giving it the means to become active. The SCLK is used by the link
to operate most of its internal circuitry. If LPS was active and then de–activated, it is a signal to the PHY chip that the
link desires entry into the power down mode. The LPSTAT bit continually indicates the status of the LPS pin and thus
the overall status of the link – PHY interface. It should also be noted here that a momentary de–activation of the LPS
signal by the setting of the RPL bit (bit 18 of register 0x004, LNKCTL) to cause a link – PHY interface reset will also
be indicated by the LPSTAT bit. It is suggested that this momentary status change be ignored when the host
controller causes a link – PHY reset through the use of the RPL bit.
Bit 19:
R/W EPLI: Enable the PHY – link initialized interrupt. Leaving this bit in the reset (0) state allows the PLI bit to be read as
a status bit.
Bit 18:
R/W ELOA: Enable link–on active interrupt. Leaving this bit in the reset (0) state allows the LOA bit to be read as a status
bit.
Bit 17:
R/W ESCA: Enable SCLK active interrupt. Leaving this bit in the reset (0) state allows the SCA bit to be read as a status
bit.
Bit 16:
R/W ESCI: Enable SCLK inactive interrupt. Leaving this bit in the reset (0) state allows the SCI bit to be read as a status
bit.
2000 Apr 15
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