PDI1394L41 Datasheet, PDF (17/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
12.5 The host interface
The host interface allows an 8 bit or 16 bit CPU to access all registers and the asynchronous packet queues. It is designed to be easy to use
with a wide range of processors, including 8051, MIPS1900, ST20, PowerPC etc. The host interface can work with 8 bit or 16 bit wide data
paths, and offers multiplexed or non-multiplexed access. There are 64 register addresses (for quadlet wide registers). To access bytes rather
than quadlets the address space is 256 bytes, requiring 8 address lines.
The use of an 8 bit or 16 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be
used (control) or changed (status) at every internal clock tick. If such a field is accessed through an 8 bit or 16 bit interface it requires more than
one read or write cycle, and the value should not change in between to maintain consistency. To overcome this problem accesses to the chip’s
internal register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit
or 16 bit accesses. This is where the shadow register (0x0F4) is used.
12.5.1 Read accesses
To read an internal register the host interface can make a snapshot (copy) of that specific register which is then made available to the CPU 8 or
16 bits at a time. The register that holds the snapshot copy of the real register value inside the host interface is called the shadow register.
During an 8-bit read cycle address lines HIF A0 and HIF A1 are used to select which of the 4 bytes currently stored in the shadow register is
output onto the CPU data bus. This selection is done by combinatorial logic only, enabling external hardware to toggle these lines through
values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an
external quadlet register. During a 16 bit read cycle address line HIF A1 is used to select which pair of 4 bytes currently stored in the shadow
register is output to the CPU bus. Again the selection is by combinatorial logic, enabling external hardware to toggle HIF A1 while keeping the
chip in read access mode to get both words very quickly.
This solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as well as the internal
address of the target register. The register address is connected to input address lines HIF A2..HIF A7, and the update control line to input
address line HIF A8. To let the host interface take a new snapshot the target address must be presented on HIF A2..HIF A7 and HIF A8 must be
raised while executing a read access. The new value will be stored in the shadow register and the selected byte (HIF A0, HIF A1, 8 bit mode)
or word (HIF A1, 16 bit mode) appears on the output.
Not all registers can be accessed in Direct Address Space. Some of the registers are in an indirect address space, these registers control the
FIFO size and content protection system. The correct internal register space has to be selected through the host interface, using directly
addressable registers INDADDR (0x0F8) and INDDATA (0x0FC).
MUX
8/16
32
CPU
TR
MUX
Q
32
Q
HIF A0..1 (8 BIT MODE)
HIF A1 (16 BIT MODE)
HIF A2..7
REGISTERS
32
HIF A8
UPDATE/COPY CONTROL
SV01034
NOTES:
1. It is not required to read all 4 bytes of a register before reading another register. For example, in 8 bit mode, if only byte 2 of register 0x54 is
required a read of byte address 0x100 + (0×54) + 2 = 0x156 is sufficient.
2. The update control line does not necessarily have to be connected to the CPU address line HIF A8. This input could also be controlled by
other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. This
makes the internal updating automatic for quadlet reading.
3. Reading the bytes of the shadow register can be done in any order and as often as needed.
4. It is possible to read/modify/write a register using the shadow register (0x0F4) without rewriting all 4 bytes. For example, to modify an enable
bit in the fourth byte of the Asynchronous Interrupt Enable (0x0A4), a read of location 0x100+0x0A0+3=0x1A3, followed by a write of the
modified byte to the same location 0x100+0x0A0+3=0x1A3 is sufficient. The other bytes remain unchanged.
2000 Apr 15
14