PDI1394L41 Datasheet, PDF (62/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
13.2.13 Isochronous Receiver Control Register (IRXCTL) – Base Address: 0x054
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPD TAG CHANNEL
ERR
SV01041
Reset Value 0x00000000
Bit 20:
R/W De-cipher Enable: When set the internal M6 cipher will decrypt the application packets with the associated key in the
M6 indirect address space for the given EMI value assigned. When the EMI value changes, the cipher will
automatically change the key on the next application packet. Changes to the ODD/EVEN bit (bit 1) will automatically
swap the odd/even key in the cipher. Note: the maximum average data rate for the M6 cipher is 60 Mbps.
Bit 17..16:
R
SPD: Speed of last received isochronous packet (S100 .. S400).
00 = 100 Mbps
01 = 200 Mbps
10 = 400 Mbps
11 = Reserved
Bit 15..14:
R/W TAG: Isochronous tag value (must match) for AV format, ‘01’ for IEC 61883 International Standard data.
Bit 13..8:
R/W CHAN: Channel number to receive isochronous data.
Bit 7..4:
R
ERR: Error code for last received isochronous AV packet.
Bit 3..2:
R
Encryption Mode Indication: This bit pattern specifies the level of copy control information for the data stream. The
field only has significance when the internal cipher is enabled (DECPHR_EN = 1). The value of these bits is stored
and accompanies the received packet through the IRx FIFO. At a later time, when the first byte of the accompanied
packet is presented at the receiving AV port, that EMI value is also presented. Note: The EMI value in this register
is indicative only of the EMI value of the packet which is being received from the bus. The EMI value at the AV port
may differ due to aging as it progresses through the IRx FIFO. See the “5C Digital Transmission Content Protection
Specification, Volume 1” for more details about EMI values.
Bit 1:
R
ODD/EVEN: Used for encryption key (0= even, 1 = odd). When the internal M6 decipher is enabled
(DECPHR_EN = 1), changes to this bit field will cause the cipher to swap its odd/even key. An interrupt will be
generated, ‘Odd/even’ in the IRXINTACK register to allow firmware to update key sets. See the “5C Digital
Transmission Content Protection Specification, Volume 1” for more details about odd/even values.
Bit 0:
R
SY: Sync code to insert in SY field of isochronous bus packet header. This bit reflects the value of the SY bit
received from the isochronous header and is synchronized in the receiver FIFO with the data payload that was
associated with it. Note: The SY value in this register is indicative only of the EMI packet which is being received
from the bus. The SY value at the AV port may differ due to aging as it progresses through the IRx FIFO.
Table 7. Error Codes
Code
Name
0000 reserved
0001 ack_complete
0010
through reserved
1100
Meaning
The node has successfully accepted the packet. If the packet was a request subaction, the destination node has
successfully completed the transaction and no response subaction shall follow.
1101
ack_data_error
The node could not accept the block packet because the data field failed the CRC check, or because the length
of the data block payload did not match the length contained in the dataLength field. this code shall not be
returned for any packet that does not have a data block payload.
1110
and
1111
reserved
2000 Apr 15
59