PDI1394L41 Datasheet, PDF (20/81 Pages) NXP Semiconductors – 1394 content protection AV link layer controller

Philips Semiconductors
1394 content protection AV link layer controller
Preliminary specification
PDI1394L41
In Little Endian mode and DATAINV = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right (least significant)
as shown in Figure 5. To access a register in 8 bit HIF mode, at address N the CPU should use addresses E:
E = N + 3 ;to access the upper 8 bits of the register
E = N + 2 ;to access the upper middle 8 bits of the register
E = N + 1 ;to access the lower middle 8 bits of the register
E = N ;to access the lower 8 bits of the register
To access a register in 16 bit HIF mode, at internal address N, the CPU should used addresses E:
E = N ;to access the lower 16 bits of the register
E = N + 2 ;to access the upper 16 bits of the register
3130 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BYTE 3
BYTE 2
BYTE 1
BYTE 0
SV01079
Figure 5. Byte order in quadlets as implemented in the host interface, HIF LTLEND = HIGH
12.5.4 Accessing the asynchronous packet queues
Although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. These buffers act like FIFOs and
only the frontmost (oldest) data quadlet entry is accessible for reading. Therefore only one location (register address) is allocated to each of the
two receiver queues. Reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the
next stored data quadlet accessible.
With the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow register. Once the data
is copied into the shadow register it is no longer available in the queue itself so the CPU should always read all 4 bytes, or both words, before
attempting any other read access (be careful with interrupt handlers for the PDI1394L41!).
2000 Apr 15
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