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NS32FX161-15 Datasheet, PDF (75/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors
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4 0 Device Specifications (Continued)
4 4 2 Timing Tables
4 4 2 1 Output Signals Internal Propagation Delays NS32FX161-15 NS32FX164-20 NS32FX164-25
 The output to input timings (e g address to data-in) are at least 2 ns better than the worst case values calculated from the
output valid and input setup times relative to CTTL
Symbol Figure
Description
Reference
Conditions
NS32FX161-15
Min Max
NS32FX164-20
Min Max
NS32FX164-25
Units
Min Max
tCTp
4-15 CTTL Clock Period
R E CTTL to Next
R E CTTL
66
1000
50
1000
40
1000 ns
tCTh
4-15 CTTL High Time
At 2 0V (Both Edges)
0 5 tCTp
b 6 ns
0 5 tCTp
b 5 ns
0 5 tCTp
b 5 ns
tCTI
4-15 CTTL Low Time
At 0 8V (Both Edges)
0 5 tCTp
b 6 ns
0 5 tCTp
b 5 ns
0 5 tCTp
b 4 ns
tCTr
4-15 CTTL Rise Time
0 8V to 2 0V
on R E CTTL
6
5
4
ns
tCTf
4-15 CTTL Fall Time
2 0V to 0 8V
on F E CTTL
6
5
4
ns
tXCTd
4-15 OSCIN to CTTL Delay 4 2V on R E
OSCIN to R E CTTL
29
29
25 ns
tXFr
4-15 OSCIN to FCLK
R E Delay
4 2V on R E OSCIN
to R E FCLK
25
20
15 ns
tFCr
4-15 FCLK to CTTL
R E Delay
R E FCLK to R E CTTL
10
10
10 ns
tFCf
4-15 FCLK to CTTL
F E Delay
R E FCLK to F E CTTL
10
10
10 ns
tALv
4-4 AD0–AD15 Valid
(Note 5)
After R E CTTL T1
14
13
12 ns
tALh
4-4 AD0–AD15 Hold
tAHv
4-4 A16–A23 Valid
(Note 5)
After R E CTTL T2
After R E CTTL T1
0
0
0
ns
14
13
12 ns
tAHh
4-4 A16–A23 Hold
After R E CTTL
Next T1 or Ti
0
0
0
ns
tALfr
4-4 AD0–AD15 Floating After R E CTTL T2
(during Read)
14
13
12 ns
tALf
4-7 AD0–AD15 Floating After R E CTTL Ti
tAHf
4-7 A16–A23 Floating
After R E CTTL Ti
tDv
4-5 Data Valid (Write Cycle) After R E CTTL
T2 or T1
14
13
12 ns
14
13
12 ns
14
13
12 ns
tDh
4-5 Data Hold
After R E CTTL
Next T1 or Ti
0
0
0
ns
tADSa
tADSia
4-4 ADS Signal Active
4-4 ADS Signal Inactive
(Note 4)
After R E CTTL T1
After R E CTTL T1
14
13
12 ns
0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp 0 5 tCTp
b6 ns a16 ns b6 ns a15 ns b6 ns a14 ns
tADSw 4-5 ADS Pulse Width
tADSf
4-7 ADS Floating
tALADSs 4-4 AD0 – AD15 Setup
tHBEv 4-4 HBE Signal Valid
tHBEh 4-4 HBE Signal Hold
At 0 8V (Both Edges)
After R E CTTL Ti
Before ADS T E
After R E CTTL T1
After R E CTTL
Next T1 or Ti
20
15
10
ns
14
13
12 ns
10
10
10
ns
14
13
12 ns
0
0
0
ns
tHBEf
4-7 HBE Signal Floating After R E CTTL Ti
14
13
12 ns
75
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