NS32FX161-15 Datasheet, PDF (74/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

4 0 Device Specifications (Continued)
4 2 ABSOLUTE MAXIMUM RATINGS
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Temperature under Bias
0 C to a70 C
Storage Temperature
b65 C to a150 C
All Input or Output Voltages
with Respect to GND
b0 5V to a6 5V
Note Absolute maximum ratings indicate limits beyond
which permanent damage may occur Continuous operation
at these limits is not intended operation should be limited to
those conditions specified under Electrical Characteristics
4 3 ELECTRICAL CHARACTERISTICS T_A e 0 C to a70 C V_CC e 5V g10% GND e 0V
Symbol
Parameter
Conditions
Min
Typ Max Units
V_IH
V_IL
V_XL
V_XH
V_RIH
V_RIL
V_RHYS
V_HYS
V_OH
V_OL
I_ILS
I_I
High Level Input Voltage
20
Low Level Input Voltage
b0 5
OSCIN Input Low Voltage
OSCIN Input High Voltage
38
RSTI High Level Input Voltage
RSTI Low Level Input Voltage
Max
(3 5 V_CC b 1 5)
b0 5
RSTI Hysteresis Loop Width (Note 3)
05
INT NMI Hysteresis Loop Width (Note 3)
02
High Level Output Voltage
Low Level Output Voltage
SPC Input Current (Low)
Input Load Current
I_OH e b400 mA
I_OL e 4 mA
V_IN e 0 4V SPC in Input Mode
0 ^s V_IN ^s V_CC
All Inputs except SPC
24
b20
V_CC a 0 5 V
08
V
05
V
V
V_CC a 0 5 V
07
V
V
V
V
0 45
V
10
mA
20
mA
I_L
Leakage Current
Output and I O Pins in
TRI-STATE or Input Mode
0 4 ^s V_OUT ^s V_CC
b20
20
mA
I_CC
Active Supply Current
I_OUT e 0 T_A e 25 C
(Note 2)
200
mA
Note 1 Care should be taken by designers to provide a minimum inductance path between the GND pins and system ground in order to minimize noise
Note 2 I_CC is affected by the clock scaling factor selected by the C- and M-bits in the CFG register see Section 3 5 3
4 4 SWITCHING CHARACTERISTICS
4 4 1 Definitions
All the timing specifications given in this section refer to
0 8V or 2 0V on the rising or falling edges of all the signals
as illustrated in Figures 4-2 and 4-3 unless specifically stat-
ed otherwise The capacitive load is assumed to be 100 pF
on CTTL and 50 pF on all the other output signals
Abbreviations
L E Leading Edge
T E Traling Edge
R E Rising Edge
F E Falling Edge
TL EE 11267–44
FIGURE 4-2 Output Signals Specification Standard
TL EE 11267 – 45
FIGURE 4-3a Input Signals Specification Standard
TL EE 11267 – 71
FIGURE 4-3b RSTI INT NMI Hysteresis
74