NS32FX161-15 Datasheet, PDF (11/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

2 0 Architectural Description (Continued)
EXT External Memory Reference Control Register
The format of the external memory reference control regis-
ter is shown in Figure 2-11
15
1
0
Reserved
HOLD
FIGURE 2-11 EXT Register Format
The EXT register controls external references The com-
mand-list execution unit checks the value of EXT HOLD be-
fore each external memory reference When EXT HOLD is
‘‘0’’ external memory references are allowed When
EXT HOLD is ‘‘1’’ and external memory references are re-
quested the execution of the command list will stop until
EXT HOLD is ‘‘0’’ Upon reset and whenever the ABORT
register is written EXT HOLD is cleared to ‘‘0’’ The EXT
register can be read or written by the core
CLSTAT Command-List Execution Status Register
The format of the command-list execution status register is
shown in Figure 2-12
15
1
0
Reserved
RUN
FIGURE 2-12 CLSTAT Register Format
The CLSTAT register displays the current status of the exe-
cution of the command list When the command-list execu-
tion is idle CLSTAT RUN is ‘‘0’’ and when it is active
CLSTAT RUN is ‘‘1’’ Upon reset the CLSTAT register is
cleared to ‘‘0’’ It can only be read and only by the core
DSPINT DSPMASK NMISTAT Interrupt Control
Registers
The format of DSPINT and DSPMASK is shown in Figure
2-13
15
1
0
Reserved
HALT
FIGURE 2-13 DSPINT and DSPMASK Register Format
The DSPINT register holds the current status of interrupt
requests Whenever execution of the command list is
stopped the DSPINT HALT bit is set to ‘‘1’’ The DSPINT is
a read only register It is cleared to ‘‘0’’ whenever it is read
whenever the ABORT register is written and upon reset
The DSPMASK register is used to mask the DSPINT HALT
flag An interrupt request is transferred to the interrupt logic
of the IOUT output pin whenever the DSPINT HALT bit is
set to ‘‘1’’ and the DSPMASK HALT bit is unmasked (set to
‘‘1’’) See Section 4 0 for the functionality of IOUT
DSPMASK can be read and written by the core Upon reset
and whenever the ABORT register is written all the bits in
DSPMASK are cleared to ‘‘0’’
The format of the NMISTAT register is shown in Figure 2-14
15
32
1
0
Reserved
ERR UND EXT
FIGURE 2-14 NMISTAT Register Format
The NMISTAT holds the status of the current pending Non-
Maskable Interrupt (NMI) requests
Whenever the core attempts to access the DSPM address
space while the CLSTAT RUN bit is ‘‘1’’ (except for access-
es to the CLSTAT EXT DSPINT NMISTAT DSPMASK
and ABORT registers) NMISTAT ERR is set to ‘‘1’’
Whenever there is an attempt to execute a DBPT instruc-
tion or a reserved DSPM instruction (Section 3 4) the
NMISTAT UND bit is set to ‘‘1’’
When a high to low transition is detected on the NMI input
pin NMISTAT EXT bit is set to ‘‘1’’
When one of the bits in NMISTAT is set to ‘‘1’’ an NMI
request to the core is issued
The NMISTAT register is cleared to 0 upon reset and each
time its contents are read
When one of the bits in NMISTAT is set to 1 an NMI occurs
The NMI handler can read the NMISTAT register to deter-
mine the source of the interrupt Note that since NMIs may
be nested it is possible that a second NMI handler (invoked
while the previous handler has not yet exited) will read and
handle more than one set bit in NMISTAT Since the read
operation clears the register the interrupted handler may
find that no bits are set
2 2 MEMORY ORGANIZATION
The main memory of the NS32FX164 is a uniform linear
address space Memory locations are numbered sequential-
ly starting at zero and ending at 2²⁴ b 1 The number speci-
fying a memory location is called an address The contents
of each memory location is a byte consisting of eight bits
Unless otherwise noted diagrams in this document show
data stored in memory with the lowest address on the right
and the highest address on the left Also when data is
shown vertically the lowest address is at the top of a dia-
gram and the highest address at the bottom of the diagram
When bits are numbered in a diagram the least significant
bit is given the number zero and is shown at the right of the
diagram Bits are numbered in increasing significance and
toward the left
7
0
A
Byte at Address A
Two contiguous bytes are called a word Except where not-
ed the least significant byte of a word is stored at the lower
address and the most significant byte of the word is stored
at the next higher address In memory the address of a
word is the address of its least significant byte and a word
may start at any address
15
87
0
Aa1
A
MSB
LSB
Word at Address A
Two contiguous words are called a double-word Except
where noted the least significant word of a double-word is
stored at the lowest address and the most significant word
of the double-word is stored at the address two higher In
memory the address of a double-word is the address of its
least significant byte and a double-word may start at any
address
31
24 23
16 15
87
0
Aa3
Aa2
Aa1
A
MSB
LSB
Double Word at Address A
11