NS32FX161-15 Datasheet, PDF (100/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

Appendix B Instruction Execution Times (Continued)
TABLE B-3 Average Instruction Execution Times with No Wait-States (Continued)
Instruction
Number of Clock Cycles
Notes
BITWT
16
28
28 a (shift b 8)
Shift e 0
x Shift e 1 8
Shift ^l 8
EXTBLT
35 a (19 a 12
35 a (13 a 12
35 a (17 a 13
35 a (11 a 13
width )
width )
width )
width )
height
height
height
height
x Shift e 0 8 Pre-Read
x Shift e 0 8 No Pre-Read
Shift ^l 8 Pre-Read
Shift ^l 8 No Pre-Read
MOVMPB W
16 a 7 R2
MOVMPD W
16 a 8 R2
SBITS
39
42
R2 ^s 25
R2 ^l 25
SBITP
8 a (34 R2)
Instruction
BBOR
BBXOR
BBAND
BBFOR
BBSTOD
BITWIT
EXTBLT
MOVMPB W
MOVMPD
SBITS
SBITP
TABLE B-4 Average Instruction Execution Times with Wait-States
Number of Clock Cycles
42 a ((107 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
44 a ((107 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
45 a ((111 a 2 Twaitblt) a (44 a Twaitblt) (width b 2)) height
48 a ((74 a 2 Twaitblt) a (32 a Twaitblt) (width b 2)) height
66 a ((170 a 2 Twaitblt) a (60 a Twaitblt) (width b 2)) height
16 a Twaitrds a Twaitrdd a Twaitwrd
28 a Twaitblt
35 a (19 a (12 a (Twaitrds a Twaitrdd a Twaitwrd) ) width ) height
35 a (13 a (12 a (Twaitrds a Twaitrdd a Twaitwrd)) width ) height
16 a 7 R2 a (Twaitwr b 1) R2
16 a 7 R2
16 a 8 R2 a Twaitwr R2
39 a (2 Twaitrdd a 2 Twaitwrd a 2 Twaitrds)
42 a (2 Twaitrdd a 2 Twaitrds)
8 a (34 R2) a ((Twaitrdd a Twaitwrd) R2)
Notes
Shift e 0
x Shift e 1 8
Pre-Read
No Pre-Read
Twaitwr ^l 1
Twaitwr ^s 1
R2 ^s 25
R2 ^l 25
B 3 DSPM INSTRUCTIONS
The performance of the command list operations is given in
the following tables
Load Register Instructions
Instruction
Cycles
LX
3
LY
3
LZ
3
LA
3
LEA
5
LPARAM
3
LREPEAT
3
LEABR
3
Store Register Instructions
Instruction
Cycles
SX
3
SXL
3
SXH
4
SY
3
SZ
3
SA
3
SEA
3
SREPEAT
3
SOVF
3
100