NS32FX161-15 Datasheet, PDF (101/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

Appendix B Instruction Execution Times (Continued)
Adjust Register Instructions
Arithmetic Logical Instructions
Instruction
Cycles
Instruction
Cycles
INCX
4
INCY
4
INCZ
4
DECX
4
DECY
4
DECZ
4
Flow Control Instructions
Instruction
Cycles
NOPR
2
HALT
1
DJNZ
5
DBPT
3
VROP
VAROP
3 c leng a 3
3 c leng a 4
Multiply-and-Accumulate Instructions
Instruction
Cycles
VRMAC
VARMAC
VCMAC
VRLATP
VCLATP
2 c leng a 7
2 c leng a 7
4 c leng a 7
4 c leng a 5
4 c leng a 2
Multiply-and-Add Instructions
Instruction
Cycles
Internal Memory Move Instructions
Instruction
Cycles
VRMOV
VARMOV
VRGATH
VRSCAT
2 c leng a 2
2 c leng a 2
4 c leng a 4
4 c leng a 4
External Memory Move Instructions
Assuming EXT HOLD e 0
Instruction
Cycles
VXLOAD
VXSTORE
VXGATH
(5 a w) leng a k a 2
(5 a w) leng a k a 2
(5 a w) leng a k a 2
w e Number of wait states in external memory access
k e Number of cycles until HLDA is received in external memory instruc-
tions
VAIMAD
VAIMADS
VRMAD
VARMAD
VEMAD
VCMAD
6 leng a 2
6 leng a 4
4 leng a 3
4 leng a 4
6 leng a 2
4 leng a 6
Clipping and Min Max Instructions
Instruction
Cycles
VARABS
VARMIN
VARMAX
VRFMIN
VRFMAX
EFMAX
2 c leng a 5
7 c leng a 2
7 c leng a 2
4 c leng a 6
4 c leng a 6
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Special Instructions
Instruction
Cycles
ESHL
VCPOLY
VDECIDE
VDIST
VFFT
VESIIR
1 c leng a 4
4 c leng a 16
12 c leng a 4
5 c leng a 5
8 c leng a 6
16 c leng a 6
If leng e 1 in ESHL instruction then the timing is 4 cycles
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