NS32FX161-15 Datasheet, PDF (34/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
FIGURE 3-8 Return from Interrupt (RETI) Instruction Flow
Direct-Exception Mode Disabled
TL EE 11267 – 21
3 2 3 Maskable Interrupts
The INT pin is a level-sensitive input A continuous low level
is allowed for generating multiple interrupt requests The in-
put is maskable and is therefore enabled to generate inter-
rupt requests only while the Processor Status Register I bit
is set The I bit is automatically cleared during service of an
INT or NMI request and is restored to its original setting
upon return from the interrupt service routine via the RETT
or RETI instruction
The INT pin may be configured via the SETCFG instruction
as either Non-Vectored (CFG Register bit I e 0) or Vec-
tored (bit I e 1)
3 2 3 1 Non-Vectored Mode
In the Non-Vectored mode an interrupt request on the INT
pin will cause an Interrupt Acknowledge bus cycle but the
CPU will ignore any value read from the bus and use instead
a default vector of zero This mode is useful for small sys-
tems in which hardware interrupt prioritization is unneces-
sary
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