NS32FX161-15 Datasheet, PDF (3/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

Table of Contents (Continued)
3 5 System Interface
3 5 1 Power and Grounding
3 5 2 Clocking
3 5 3 Power Save Mode
3 5 4 Resetting
3 5 5 Bus Cycles
3 5 5 1 Bus Status
3 5 5 2 Basic Read and Write Cycles
3 5 5 3 Cycle Extension
3 5 5 4 Instruction Fetch Cycles
3 5 5 5 Interrupt Control Cycles
3 5 5 6 Special Bus Cycles
3 5 5 7 Slave Processor Bus Cycles
3 5 5 8 Data Access Sequences
3 5 5 9 Bus Access Control
3 5 5 10 Instruction Status
4 0 DEVICE SPECIFICATIONS
4 1 NS32FX164 Pin Descriptions
4 1 1 Supplies
4 1 2 Input Signals
4 1 3 Output Signals
4 1 4 Input-Output Signals
55
4 2 Absolute Maximum Ratings
74
55
4 3 Electrical Characteristics
74
56
4 4 Switching Characteristics
74
57
4 4 1 Definitions
74
57
4 4 2 Timing Tables
75
58
4 4 2 1 Output Signals Internal Propagation
58
Delays
75
58
4 4 2 2 Input Signal Requirements
77
62
4 4 3 Timing Diagrams
79
63
APPENDIX A INSTRUCTION FORMATS
89
64
65
APPENDIX B INSTRUCTION EXECUTION TIMES 92
65
B 1 Basic and Floating-Point Instructions
92
67
B 1 1 Equations
92
68
B 1 2 Notes on Table Use
93
71
B 1 3 Calculation of the Execution Time TEX for Basic
71
Instructions
93
71
B 1 4 Calculation of the Execution Time TEX for
71
Floating-Point Instructions
93
71
B 2 Special Graphics Instructions
99
71
B 2 1 Execution Time Calculation for Special
72
Graphics Instructions
99
B 3 DSPM Instructions
100
List of Figures
FIGURE 1-1 CPU Block Diagram
1
FIGURE 2-1 NS32FX164 Internal Registers
7
FIGURE 2-2 Processor Status Register (PSR)
8
FIGURE 2-3 Configuration Register (CFG)
9
FIGURE 2-4 DSP Module Registers Address Map
9
FIGURE 2-5 Accumulator Format
9
FIGURE 2-6 X Y Z Registers Format
9
FIGURE 2-7 EABR Register Format
10
FIGURE 2-8 OVF Register Format
10
FIGURE 2-9 PARAM Register Format
10
FIGURE 2-10 REPEAT Register Format
10
FIGURE 2-11 EXT Register Format
11
FIGURE 2-12 CLSTAT Register Format
11
FIGURE 2-13 DSPINT and DSPMASK Register Format
11
FIGURE 2-14 NMISTAT Register Format
11
FIGURE 2-15 NS32FX164 Address Mapping
12
FIGURE 2-16 NS32FX164 Run-Time Environment
13
FIGURE 2-17 General Instruction Format
13
FIGURE 2-18 Index Byte Format
13
FIGURE 2-19 Displacement Encodings
14
FIGURE 2-20 Correspondence between Linear and Cartesian Addressing
20
FIGURE 2-21 32-Pixel by 32-Scan Line Frame Buffer
21
FIGURE 2-22 Overlapping BITBLT Blocks
22
FIGURE 2-23 BB Instructions Format
23
FIGURE 2-24 BITWT Instruction Format
24
FIGURE 2-25 EXTBLT Instruction Format
24
FIGURE 2-26 MOVMPi Instruction Format
24
3