NS32FX161-15 Datasheet, PDF (4/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

List of Figures (Continued)
FIGURE 2-27 TBITS Instruction Format
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FIGURE 2-28 SBITS Instruction Format
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FIGURE 2-29 SBITPS Instruction Format
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FIGURE 2-30 Bus Activity for a Simple BITBLT Operation
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FIGURE 3-1 Operating States
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FIGURE 3-2 Slave Processor Protocol
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FIGURE 3-3 Slave Processor Status Word
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FIGURE 3-4 Interrupt Dispatch and Cascade Tables
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FIGURE 3-5 Exception Acknowledge Sequence Direct-Exception Mode Disabled
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FIGURE 3-6 Exception Acknowledge Sequence Direct-Exception Mode Enabled
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FIGURE 3-7 Return from Trap (RETTn) Instruction Flow Direct-Exception Mode Disabled
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FIGURE 3-8 Return from Interrupt (RETI) Instruction Flow Direct-Exception Mode Disabled
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FIGURE 3-9 Interrupt Control Unit Connections (16 Levels)
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FIGURE 3-10 Cascaded Interrupt Control Unit Connections
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FIGURE 3-11 Exception Processing Flowchart
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FIGURE 3-12 Service Sequence
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FIGURE 3-13 DSP Module Block Diagram
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FIGURE 3-14 Power and Ground Connections
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FIGURE 3-15 Crystal Interconnections 30 MHz
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FIGURE 3-16 Crystal Interconnections 40 MHz 50 MHz
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FIGURE 3-17 Recommended Reset Connections
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FIGURE 3-18 Power-On Reset Requirements
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FIGURE 3-19 General Reset Timing
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FIGURE 3-20 Bus Connections
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FIGURE 3-21 Read Cycle Timing
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FIGURE 3-22 Write Cycle Timing
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FIGURE 3-23 Cycle Extension of a Read Cycle
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FIGURE 3-24 Special Bus Cycle Timing
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FIGURE 3-25 Slave Processor Read Cycle
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FIGURE 3-26 Slave Processor Write Cycle
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FIGURE 3-27 NS32FX164 and FPU Interconnections
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FIGURE 3-28 Memory Interface
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FIGURE 3-29 HOLD Timing (Bus Initially Idle)
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FIGURE 3-30 HOLD Timing (Bus Initially Not Idle)
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FIGURE 4-1 Connection Diagram
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FIGURE 4-2 Output Signals Specification Standard
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FIGURE 4-3a Input Signals Specification Standard
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FIGURE 4-3b RSTI INT NMI Hysteresis
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FIGURE 4-4 Read Cycle
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FIGURE 4-5 Write Cycle
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FIGURE 4-6 Special Bus Cycle
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FIGURE 4-7 HOLD Acknowledge Timing (Bus Initially Not Idle)
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FIGURE 4-8 HOLD Timing (Bus Initially Idle)
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FIGURE 4-9 External DMA Controller Bus Cycle
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FIGURE 4-10 Slave Processor Write Timing
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FIGURE 4-11 Slave Processor Read Timing
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FIGURE 4-12 SPC Timing
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FIGURE 4-13 PFS Signal Timing
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FIGURE 4-14 ILO Signal Timing
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FIGURE 4-15 Clock Waveforms
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FIGURE 4-16 INT Signal Timing
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