NS32FX161-15 Datasheet, PDF (66/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
Note CPU samples Data Bus here
FIGURE 3-25 Slave Processor Read Cycle
TL EE 11267 – 37
The CPU does not pulse the Address Strobe (ADS) and no
bus signals are generated The direction of a transfer is de-
termined by the sequence (‘‘protocol’’) established by the
instruction under execution but the CPU indicates the direc-
tion on the DDIN pin for hardware debugging purposes
A Slave Processor operand is transferred in one or more
Slave bus cycles A Byte operand is transferred on the
least-significant byte of the Data Bus (AD0–AD7) and a
Word operand is transferred on the entire bus A Double
Word is transferred in a consecutive pair of bus cycles
least-significant word first A Quad Word is transferred in
two pairs of Slave cycles with other bus cycles possibly
occurring between them The word order is from least-signif-
icant word to most-significant
Figure 3-27 shows the NS32FX164 and FPU connection di-
agram
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