NS32FX161-15 Datasheet, PDF (69/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
How quickly the CPU releases the bus depends on whether
it is idle on the bus at the time the HOLD request is made
as the CPU must always complete the current bus cycle
Figure 3-29 shows the timing sequence when the CPU is
idle In this case the CPU grants the bus during the immedi-
ately following clock cycle Figure 3-30 shows the sequence
when the CPU is using the bus at the time the HOLD re-
quest is made If the request is made during or before the
clock cycle shown (two clock cycles before T4) the CPU
will release the bus during the clock cycle following T4 If
the request occurs closer to T4 the CPU may already have
decided to initiate another bus cycle In that case it will not
grant the bus until after the next T4 state Note that this
situation will also occur if the CPU is idle on the bus but has
initiated a bus cycle internally
Note 1 The logic value of the status pins ST0–3 is undefined during DMA
activity
FIGURE 3-29 HOLD Timing (Bus Initially Idle)
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