NS32FX161-15 Datasheet, PDF (45/102 Pages) National Semiconductor (TI) – Advanced Imaging/Communication Signal Processors

3 0 Functional Description (Continued)
LA Load Accumulator
The LA instruction loads the complex value at aligned
addr into the A accumulator as a complex value
Syntax
LA aligned addr
15
11 10
0
00101
aligned addr
Operation
(complex) A 4 (complex) mem aligned addr
Notes The real and imaginary parts are placed in bits 15 through 30 of the
real and imaginary parts of the accumulator
When PARAM RND is set to ‘‘1’’ bit 14 of the real and imaginary
parts is set to ‘‘1’’ in order to implement rounding upon subsequent
additions into the accumulator Otherwise it is cleared to ‘‘0’’
LEA Load Extended Accumulator
The LEA instruction loads the accumulator with the extend-
ed value specified by X 0
Both the real and the imaginary parts of the accumulator are
loaded
Syntax
EXEC LEA
15
10000
Operation
11 10
0
101 0011 0011
extended X
A 4 (extended) X 0
Note Bits 1 through 31 of the memory location are read into bit positions 0
through 30 of the accumulator
LPARAM Load Parameters Register
The LPARAM instruction loads the double-word at
aligned addr into the PARAM register
Syntax
LPARAM aligned addr
15
00000
Operation
11 10
0
aligned addr
PARAM 4 (param reg) mem aligned addr
Notes The value at mem aligned addr should conform to this register
format The value written into PARAM LENGTH must be greater
then 0
Accumulator is not affected
LREPEAT Load Repeat Register
The LREPEAT instruction loads the double-word at
aligned addr into the REPEAT register
Syntax
LREPEAT aligned addr
15
00110
Operation
11 10
0
aligned addr
REPEAT 4 (repeat reg) mem aligned addr
Notes The value at mem aligned addr should conform to the REPEAT
register format
Accumulator is not affected
LEABR Load External Address Base Register
The LEABR instruction loads the double-word at
mem aligned addr into the EABR register
Syntax
LEABR aligned addr
15
00111
Operation
11 10
0
aligned addr
EABR 4 (eabr reg) mem aligned addr
Notes The value at mem aligned addr should conform to vector pointer
specification format that is bit positions 0 through 16 must be speci-
fied as ‘‘0’
Accumulator is not affected
3 4 5 5 Store Register Instructions
SX Store X Vector Pointer
The SX instruction stores the contents of the X register into
the double-word at aligned addr
Syntax
SX aligned addr
15
01010
Operation
11 10
0
aligned addr
(vector ptr) mem aligned addr 4 X
Note Accumulator is not affected
SXL Store X Vector Pointer Lower Half
The SXL instruction stores the contents of the lower-half of
the X register into the word at mem addr
Syntax
SXL addr
15
11 10
0
11100
addr
Operation
mem aligned addr 4 X low
Note Accumulator is not affected
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